summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* AMDGPU: Split LDS vector loadsMatt Arsenault2015-11-242-2/+3
| | | | | | If properly aligned this could allow using ds_read_b64. llvm-svn: 253975
* AMDGPU: Split x8 and x16 vector loads instead of scalarizeMatt Arsenault2015-11-242-1/+15
| | | | | | | | The one regression in the builtin tests is in the read2 test which now (again) has many extra copies, but this should be solved once the pass is replaced with a DAG combine. llvm-svn: 253974
* Let SelectionDAG start to use probability-based interface to add successors.Cong Hou2015-11-244-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | The patch in http://reviews.llvm.org/D13745 is broken into four parts: 1. New interfaces without functional changes. 2. Use new interfaces in SelectionDAG, while in other passes treat probabilities as weights. 3. Use new interfaces in all other passes. 4. Remove old interfaces. This the second patch above. In this patch SelectionDAG starts to use probability-based interfaces in MBB to add successors but other MC passes are still using weight-based interfaces. Therefore, we need to maintain correct weight list in MBB even when probability-based interfaces are used. This is done by updating weight list in probability-based interfaces by treating the numerator of probabilities as weights. This change affects many test cases that check successor weight values. I will update those test cases once this patch looks good to you. Differential revision: http://reviews.llvm.org/D14361 llvm-svn: 253965
* [X86][SSE] Detect AVG pattern during instruction combine for SSE2/AVX2/AVX512BW.Cong Hou2015-11-243-4/+176
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch detects the AVG pattern in vectorized code, which is simply c = (a + b + 1) / 2, where a, b, and c have the same type which are vectors of either unsigned i8 or unsigned i16. In the IR, i8/i16 will be promoted to i32 before any arithmetic operations. The following IR shows such an example: %1 = zext <N x i8> %a to <N x i32> %2 = zext <N x i8> %b to <N x i32> %3 = add nuw nsw <N x i32> %1, <i32 1 x N> %4 = add nuw nsw <N x i32> %3, %2 %5 = lshr <N x i32> %N, <i32 1 x N> %6 = trunc <N x i32> %5 to <N x i8> and with this patch it will be converted to a X86ISD::AVG instruction. The pattern recognition is done when combining instructions just before type legalization during instruction selection. We do it here because after type legalization, it is much more difficult to do pattern recognition based on many instructions that are doing type conversions. Therefore, for target-specific instructions (like X86ISD::AVG), we need to take care of type legalization by ourselves. However, as X86ISD::AVG behaves similarly to ISD::ADD, I am wondering if there is a way to legalize operands and result types of X86ISD::AVG together with ISD::ADD. It seems that the current design doesn't support this idea. Tests are added for SSE2, AVX2, and AVX512BW and both i8 and i16 types of variant vector sizes. Differential revision: http://reviews.llvm.org/D14761 llvm-svn: 253952
* [WebAssembly] Don't print the types of memory_size and grow_memoryDan Gohman2015-11-231-4/+4
| | | | | | This matches the current spec, for now. llvm-svn: 253931
* findDeadCallerSavedReg needs to pay attention to calling conventionAndy Ayers2015-11-234-24/+26
| | | | | | | | | | Caller saved regs differ between SysV and Win64. Use the tail call available set to scavenge from. Refactor register info to create new helper to get at tail call GPRs. Added a new test case for windows. Fixed up a number of X64 tests since now RCX is preferred over RDX on SysV. Differential Revision: http://reviews.llvm.org/D14878 llvm-svn: 253927
* [WebAssembly] Don't special-case call operand order.Dan Gohman2015-11-231-2/+2
| | | | | | | | With the '=' suffix now indicating which operands are output operands, it's no longer as important to distinguish between a call's inputs and its outputs using operand ordering, so we can go back to printing them in the normal order. llvm-svn: 253925
* [WebAssembly] Suffix output operands with '='.Dan Gohman2015-11-231-0/+3
| | | | | | | | This distinguishes input operands from output operands. This is something of a syntactic experiment to see whether the mild amount of clutter this adds is outweighed by the extra information it conveys to the reader. llvm-svn: 253922
* [WebAssembly] Model the return value of store instructions in wasm.Dan Gohman2015-11-232-27/+41
| | | | llvm-svn: 253916
* [WebAssembly] Don't use set_local instructions explicitly.Dan Gohman2015-11-232-6/+14
| | | | | | | | | The current approach to using get_local and set_local is to use them implicitly, as register uses and defs. Introduce new copy instructions which are themselves no-ops except for the get_local and set_local that they imply, so that we use get_local and set_local consistently. llvm-svn: 253905
* [WebAssembly] Always print loop end labelsDan Gohman2015-11-233-1/+20
| | | | | | | | | | | | | | | | | WebAssembly is currently using labels to end scopes, so for example a loop scope looks like this: BB0_0: loop BB0_1 ... BB0_1: with BB0_0 being the label of the first block not in the loop. This requires that the label be printed even when it's only reachable via fallthrough. To arrange this, insert a no-op LOOP_END instruction in such cases at the end of the loop. llvm-svn: 253901
* [WebAssembly] Remove incomplete MCCodeEmitter bits.Dan Gohman2015-11-232-4/+0
| | | | | | These are parts of a separate patch that I accidentally included in r253878. llvm-svn: 253892
* [WebAssembly] Emit .param, .result, and .local through MC.Dan Gohman2015-11-237-28/+63
| | | | | | This eliminates one of the main remaining uses of EmitRawText. llvm-svn: 253878
* [WebAssembly] Use dominator information to improve BLOCK placementDan Gohman2015-11-231-46/+125
| | | | | | | | | | Always starting blocks at the top of their containing loops works, but creates unnecessarily deep nesting because it makes all blocks in a loop overlap. Refine the BLOCK placement algorithm to start blocks at nearest common dominating points instead, which significantly shrinks them and reduces overlapping. llvm-svn: 253876
* [mips] .ent and .end should also set the type and size of the symbol ↵Daniel Sanders2015-11-231-1/+17
| | | | | | | | | | | | respectively. Reviewers: vkalintiris Subscribers: llvm-commits, seanbruno, emaste, vkalintiris, dsanders Differential Revision: http://reviews.llvm.org/D14221 llvm-svn: 253875
* [Hexagon] Update instruction formatsKrzysztof Parzyszek2015-11-234-35/+41
| | | | llvm-svn: 253867
* ARM: address WoA division overflow crashMartell Malone2015-11-232-23/+14
| | | | | | | Disable custom handling of signed 32-bit and 64-bit integer divide. Add test cases for both 32-bit and 64-bit integer overflow crashes. llvm-svn: 253865
* [Mips] Remove an unnecessary wrapping of a predicate with std::ptr_fun. NFCCraig Topper2015-11-231-1/+1
| | | | llvm-svn: 253855
* AVX-512: Optimized INSERT_SUBVECTOR for i1 vector typesElena Demikhovsky2015-11-222-60/+154
| | | | | | | | | ISERT_SUBVECTOR for i1 vectors may be done with shifts, when we insert into the lower part, or into the upper part, on into all-zero vector. CONCAT_VECTORS uses ISERT_SUBVECTOR. Differential Revision: http://reviews.llvm.org/D14815 llvm-svn: 253819
* fix formatting; NFCSanjay Patel2015-11-221-5/+5
| | | | llvm-svn: 253802
* Hexagon V60/HVX DFA scheduler supportKrzysztof Parzyszek2015-11-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extended DFA tablegen to: - added "-debug-only dfa-emitter" support to llvm-tblgen - defined CVI_PIPE* resources for the V60 vector coprocessor - allow specification of multiple required resources - supports ANDs of ORs - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means: (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1) - added support for combo resources - allows specifying ORs of ANDs - e.g. [CVI_XLSHF, CVI_MPY01] means: (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1) - increased DFA input size from 32-bit to 64-bit - allows for a maximum of 4 AND'ed terms of 16 resources - supported expressions now include: expression => term [AND term] [AND term] [AND term] term => resource [OR resource]* resource => one_resource | combo_resource combo_resource => (one_resource [AND one_resource]*) Author: Dan Palermo <dpalermo@codeaurora.org> kparzysz: Verified AMDGPU codegen to be unchanged on all llc tests, except those dealing with instruction encodings. Reapply the previous patch, this time without circular dependencies. llvm-svn: 253793
* Revert r253790: it breaks all builds for some reason.Krzysztof Parzyszek2015-11-211-9/+0
| | | | llvm-svn: 253791
* Hexagon V60/HVX DFA scheduler supportKrzysztof Parzyszek2015-11-211-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Extended DFA tablegen to: - added "-debug-only dfa-emitter" support to llvm-tblgen - defined CVI_PIPE* resources for the V60 vector coprocessor - allow specification of multiple required resources - supports ANDs of ORs - e.g. [SLOT2, SLOT3], [CVI_MPY0, CVI_MPY1] means: (SLOT2 OR SLOT3) AND (CVI_MPY0 OR CVI_MPY1) - added support for combo resources - allows specifying ORs of ANDs - e.g. [CVI_XLSHF, CVI_MPY01] means: (CVI_XLANE AND CVI_SHIFT) OR (CVI_MPY0 AND CVI_MPY1) - increased DFA input size from 32-bit to 64-bit - allows for a maximum of 4 AND'ed terms of 16 resources - supported expressions now include: expression => term [AND term] [AND term] [AND term] term => resource [OR resource]* resource => one_resource | combo_resource combo_resource => (one_resource [AND one_resource]*) Author: Dan Palermo <dpalermo@codeaurora.org> kparzysz: Verified AMDGPU codegen to be unchanged on all llc tests, except those dealing with instruction encodings. llvm-svn: 253790
* [X86][AVX512] Added AVX512 VMOVLHPS/VMOVHLPS shuffle decode comments.Simon Pilgrim2015-11-211-0/+3
| | | | llvm-svn: 253777
* [X86][SSE] Legal XMM Register Class ordering for SSE1Simon Pilgrim2015-11-211-4/+5
| | | | | | | | | | | | It turns out we have a number of places that just grab the first type attached to a register class for various reasons. This is fine unless for some reason that type isn't legal on the current target, such as for SSE1 which doesn't support v16i8/v8i16/v4i32/v2i64 - all of which were included before 4f32 in the class. Given that this is such a rare situation I've just re-ordered the types and placed the float types first. Fix for PR16133 Differential Revision: http://reviews.llvm.org/D14787 llvm-svn: 253773
* ARMLoadStoreOptimizer: Cleanup isMemoryOp(); NFCMatthias Braun2015-11-211-33/+33
| | | | llvm-svn: 253757
* Test commitVinicius Tinti2015-11-201-4/+4
| | | | llvm-svn: 253737
* Power8 and later support fusing addis/addi and addis/ld instructionEric Christopher2015-11-203-1/+7
| | | | | | | | | pairs that use the same register to execute as a single instruction. No Functional Change Patch by Kyle Butt! llvm-svn: 253724
* [AArch64]Merge narrow zero stores to a wider storeJun Bum Lim2015-11-201-16/+80
| | | | | | | | | | | | | This change merges adjacent zero stores into a wider single store. For example : strh wzr, [x0] strh wzr, [x0, #2] becomes str wzr, [x0] This will fix PR25410. llvm-svn: 253711
* Weak non-function symbols were being accessed directly, which isEric Christopher2015-11-205-47/+64
| | | | | | | | | | incorrect, as the chosen representative of the weak symbol may not live with the code in question. Always indirect the access through the TOC instead. Patch by Kyle Butt! llvm-svn: 253708
* [Hexagon] Fix the return value from HexagonGenInsert::runOnMachineFunctionKrzysztof Parzyszek2015-11-201-5/+7
| | | | llvm-svn: 253705
* Handle ARMv6-J as an alias, instead of fake architectureArtyom Skrobov2015-11-201-1/+0
| | | | | | | | | | | | | | | | | | | | | | Summary: This follows D14577 to treat ARMv6-J as an alias for ARMv6, instead of an architecture in its own right. The functional change is that the default CPU when targeting ARMv6-J changes from arm1136j-s to arm1136jf-s, which is currently used as the default CPU for ARMv6; both are, in fact, ARMv6-J CPUs. The J-bit (Jazelle support) is irrelevant to LLVM, and it doesn't affect code generation, attributes, optimizations, or anything else, apart from selecting the default CPU. Reviewers: rengolin, logan, compnerd Subscribers: aemerson, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D14755 llvm-svn: 253675
* [Hexagon] Remove redundant assignment.Tilmann Scheller2015-11-201-1/+1
| | | | | | Identified by the Clang static analyzer. llvm-svn: 253664
* Partially revert r253662: some unrelated work was accidentally committed ↵Daniel Sanders2015-11-201-19/+8
| | | | | | | | with it. Sorry. llvm-svn: 253663
* Revert the revert 253497 and 253539 - These commits aren't the cause of the ↵Daniel Sanders2015-11-201-8/+19
| | | | | | | | clang-cmake-mips failures. Sorry for the noise. llvm-svn: 253662
* [Hexagon] Remove redundant local variable.Tilmann Scheller2015-11-201-4/+2
| | | | | | Identified by the Clang static analyzer. llvm-svn: 253660
* [mips][microMIPS] Implement MUL[_S].PH, MULEQ_S.W.PHL, MULEQ_S.W.PHR, ↵Hrvoje Varga2015-11-202-10/+30
| | | | | | | | MULEU_S.PH.QBL, MULEU_S.PH.QBR, MULQ_RS.PH, MULQ_RS.W, MULQ_S.PH and MULQ_S.W instructions Differential Revision: http://reviews.llvm.org/D14280 llvm-svn: 253651
* [WebAssembly] Remove the AsmPrinter code for printing physical registers.Dan Gohman2015-11-201-3/+2
| | | | | | | | WebAssembly does not have physical registers, so even if LLVM uses physical registers like SP, they'll need to be lowered to virtual registers before AsmPrinter time. llvm-svn: 253644
* [WebAssembly] Add a few open tasks to the target README.txt.Dan Gohman2015-11-201-0/+17
| | | | llvm-svn: 253643
* [WebAssembly] Rename SWITCH to TABLESWITCH to match the current wording in ↵Dan Gohman2015-11-204-15/+15
| | | | | | the spec. llvm-svn: 253642
* [WebAssembly] Remove done items from the README.txt.Dan Gohman2015-11-201-3/+0
| | | | llvm-svn: 253640
* [WebAssembly] Add asserts that the expression stack is used in stack order.Dan Gohman2015-11-201-0/+23
| | | | llvm-svn: 253638
* [WebAssemby] Enforce FIFO ordering for instructions using stackified registers.Dan Gohman2015-11-202-0/+30
| | | | llvm-svn: 253634
* Split the argument unscheduling loop in the WebAssembly registerEric Christopher2015-11-201-8/+18
| | | | | | | | | coloring pass. Turn the logic into "look for an insert point and then move things past the insert point". No functional change intended. llvm-svn: 253626
* Fix a [-Werror,-Wcovered-switch-default] warning by removing theEric Christopher2015-11-191-1/+0
| | | | | | unnecessary default case. llvm-svn: 253621
* [WebAssembly] Implement isCheapToSpeculateCtlz and isCheapToSpeculateCttz.Dan Gohman2015-11-192-0/+12
| | | | | | | This unbreaks test/CodeGen/WebAssembly/i32.ll and test/CodeGen/WebAssembly/i64.ll after r224899. llvm-svn: 253617
* [X86][SSE4A] Fix issue with EXTRQI shuffles not starting at the correct ↵Simon Pilgrim2015-11-191-2/+3
| | | | | | | | start index. Found during stress testing. llvm-svn: 253611
* Fix UMRs in Mips disassembler on invalid instruction streamsReid Kleckner2015-11-191-1/+9
| | | | | | The Insn and Size local variables were used without initialization. llvm-svn: 253607
* [X86] Use existing MachineInstrBuilder::addDisp to create offseted pointer. NFC.Simon Pilgrim2015-11-191-8/+1
| | | | | | Minor code duplication tidyup to D13988 llvm-svn: 253606
* [AArch64] Refactoring aarch64-ldst-opt. NCF.Jun Bum Lim2015-11-191-16/+13
| | | | | | | | | Summary : * Rename isSmallTypeLdMerge() to isNarrowLoad(). * Rename NumSmallTypeMerged to NumNarrowTypePromoted. * Use Subtarget defined as a member variable. llvm-svn: 253587
OpenPOWER on IntegriCloud