summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* Use cbz and cbnz instructions.Evan Cheng2009-10-312-11/+62
| | | | llvm-svn: 85698
* vml[as].f32 cause stalls in following advanced SIMD instructions. Avoid usingJim Grosbach2009-10-311-6/+9
| | | | | | them for scalar floating point operations for now. llvm-svn: 85697
* Expand 64-bit logical shift right inlineJim Grosbach2009-10-311-4/+7
| | | | llvm-svn: 85687
* Expand 64-bit arithmetic shift right inlineJim Grosbach2009-10-311-1/+36
| | | | llvm-svn: 85685
* Expand 64 bit left shift inline rather than using the libcall. For now, thisJim Grosbach2009-10-311-1/+36
| | | | | | | is unconditional. Making it still use the libcall when optimizing for size would be a good adjustment. llvm-svn: 85675
* It's safe to remat t2LDRpci; Add PseudoSourceValue to load / store's to ↵Evan Cheng2009-10-312-15/+31
| | | | | | enable more machine licm. More changes coming. llvm-svn: 85643
* Updates to the ARM target assembler for llvm-mc per review comments fromKevin Enderby2009-10-301-135/+134
| | | | | | | | | | | | | | | | | | Daniel Dunbar. - Reordered the fields in the ARMOperand Mem struct to make the struct smaller. Making bool's into 1 bit fields and put the MCExpr* fields adjacent to each other. - Fixed a number of places in ARMAsmParser.cpp so they have doxygen comments. - Change the name of ARMAsmParser::ParseRegister() to MaybeParseRegister and added the bool ParseWriteBack parameter. - Changed ARMAsmParser::ParseMemory() to call MaybeParseRegister(). - Added ARMAsmParser::ParseMemoryOffsetReg to factor out parsing the offset of a memory operand. And use it for both parsing both preindexed and post indexing addressing forms in ARMAsmParser::ParseMemory. - Changed the first argument to ParseShift() to a reference. - Changed ParseShift() to check for Rrx first and return to reduce nesting. llvm-svn: 85632
* Add a note about Robert Muth's alternate jump table implementation.Bob Wilson2009-10-301-0/+9
| | | | llvm-svn: 85624
* Fix MachineLICM to use the correct virtual register class whenDan Gohman2009-10-302-3/+9
| | | | | | | | | | unfolding loads for hoisting. getOpcodeAfterMemoryUnfold returns the opcode of the original operation without the load, not the load itself, MachineLICM needs to know the operand index in order to get the correct register class. Extend getOpcodeAfterMemoryUnfold to return this information. llvm-svn: 85622
* Fix a comment.Bob Wilson2009-10-301-1/+1
| | | | llvm-svn: 85610
* This fixes functions likeRafael Espindola2009-10-301-2/+1
| | | | | | | | | | | void f (int a1, int a2, int a3, int a4, int a5,...) In ARMTargetLowering::LowerFormalArguments if the function has 4 or more regular arguments we used to set VarArgsFrameIndex using an offset of 0, which is only correct if the function has exactly 4 regular arguments. llvm-svn: 85590
* Add ARM codegen for indirect branches.Bob Wilson2009-10-306-6/+23
| | | | | | clang/test/CodeGen/indirect-goto.c runs! (unoptimized) llvm-svn: 85577
* Initial x86 support for BlockAddresses.Dan Gohman2009-10-305-0/+40
| | | | llvm-svn: 85557
* Dial back the realignment a bit.Jim Grosbach2009-10-301-9/+3
| | | | llvm-svn: 85546
* Rename usesCustomDAGSchedInserter to usesCustomInserter, and update aDan Gohman2009-10-2918-44/+42
| | | | | | | | bunch of associated comments, because it doesn't have anything to do with DAGs or scheduling. This is another step in decoupling MachineInstr emitting from scheduling. llvm-svn: 85517
* To get more thorough testing from llc-beta nightly runs, do dynamic stackJim Grosbach2009-10-291-4/+9
| | | | | | realignment regardless of whether it's strictly necessary. llvm-svn: 85476
* Revert r85346 change to control tail merging by CodeGenOpt::Level.Bob Wilson2009-10-281-1/+1
| | | | | | I'm going to redo this using the OptimizeForSize function attribute. llvm-svn: 85426
* Add a Thumb BRIND pattern. Change the ARM BRIND assembly to separate theBob Wilson2009-10-287-2/+17
| | | | | | | opcode and operand with a tab. Check for these instructions in the usual places. llvm-svn: 85411
* fconsts and fconstd are obviously re-materializable.Evan Cheng2009-10-281-0/+2
| | | | llvm-svn: 85410
* Cleanup now that frame index scavenging via post-pass is working for ARM and ↵Jim Grosbach2009-10-285-53/+4
| | | | | | Thumb2. llvm-svn: 85406
* Give ARMISD::EH_SJLJ_LONGJMP and EH_SJLJ_SETJMP names.Evan Cheng2009-10-281-0/+3
| | | | llvm-svn: 85381
* X86 palignr intrinsics immediate field is in bits. ISel must transform it ↵Evan Cheng2009-10-281-24/+29
| | | | | | into bytes. llvm-svn: 85379
* Previously, all operands to Constant were themselves constant.Chris Lattner2009-10-281-1/+1
| | | | | | | | | In the new world order, BlockAddress can have a BasicBlock operand. This doesn't permute much, because if you have a ConstantExpr (or anything more specific than Constant) we still know the operand has to be a Constant. llvm-svn: 85375
* Use fconsts and fconstd to materialize small fp constants.Evan Cheng2009-10-285-6/+149
| | | | llvm-svn: 85362
* Add a second ValueType argument to isFPImmLegal.Evan Cheng2009-10-288-9/+13
| | | | llvm-svn: 85361
* Update SystemZ to use PSW following the way x86 uses EFLAGS. BesidesDan Gohman2009-10-283-30/+36
| | | | | | | | | | | eliminating a use of MVT::Flag, this is needed for an upcoming CodeGen change. This unfortunately requires SystemZ to switch to the list-burr scheduler, in order to handle the physreg defs properly, however that's what LLVM has available at this time. llvm-svn: 85357
* Add an indirect branch pattern for ARM. Testcase will be coming soon.Bob Wilson2009-10-281-0/+10
| | | | llvm-svn: 85355
* rename indbr -> indirectbr to appease the residents of #llvm.Chris Lattner2009-10-282-5/+5
| | | | llvm-svn: 85351
* Record CodeGen optimization level in the BranchFolding pass so that we canBob Wilson2009-10-271-1/+1
| | | | | | | | | | | | | | | | use it to control tail merging when there is a tradeoff between performance and code size. When there is only 1 instruction in the common tail, we have been merging. That can be good for code size but is a definite loss for performance. Now we will avoid tail merging in that case when the optimization level is "Aggressive", i.e., "-O3". Radar 7338114. Since the IfConversion pass invokes BranchFolding, it too needs to know the optimization level. Note that I removed the RegisterPass instantiation for IfConversion because it required a default constructor. If someone wants to keep that for some reason, we can add a default constructor with a hard-wired optimization level. llvm-svn: 85346
* Add new note.Bill Wendling2009-10-271-0/+35
| | | | llvm-svn: 85341
* Enable virtual register based frame index scavenging by default for ARM & T2.Jim Grosbach2009-10-271-2/+2
| | | | llvm-svn: 85335
* Move and clarify note.Bill Wendling2009-10-272-31/+33
| | | | llvm-svn: 85334
* Infrastructure for dynamic stack realignment on ARM. For now, this is off byJim Grosbach2009-10-272-2/+76
| | | | | | | default behind a command line option. This will enable better performance for vectors on NEON enabled processors. llvm-svn: 85333
* Note corrected.Bill Wendling2009-10-271-3/+5
| | | | llvm-svn: 85332
* Modify note.Bill Wendling2009-10-271-0/+8
| | | | llvm-svn: 85331
* Add a note.Bill Wendling2009-10-271-0/+23
| | | | llvm-svn: 85329
* cppbackend support for indbrChris Lattner2009-10-271-3/+14
| | | | llvm-svn: 85312
* CBE support for indbr.Chris Lattner2009-10-271-0/+7
| | | | llvm-svn: 85311
* Similar to r85280, do not clear the "S" bit for RSBri and RSBrs.Johnny Chen2009-10-271-2/+0
| | | | llvm-svn: 85299
* Set condition code bits of BL and BLr9 to 0b1110 (ALways) to distinguish betweenJohnny Chen2009-10-271-2/+6
| | | | | | BL_pred and BLr9_pred. llvm-svn: 85297
* Do away with addLegalFPImmediate. Add a target hook isFPImmLegal which ↵Evan Cheng2009-10-278-13/+63
| | | | | | returns true if the fp immediate can be natively codegened by target. llvm-svn: 85281
* Do not clear the "S" bit for RSCri and RSCrs. They inherit from the "sI"Bob Wilson2009-10-271-2/+0
| | | | | | instruction format that already takes care of setting this. llvm-svn: 85280
* Explicitly specify 0b00, i.e, zero rotation, as the rotate filed (Inst{11-10})Johnny Chen2009-10-271-5/+8
| | | | | | for the r/rr fragment of the multiclass AI_unary_rrot/AI_bin_rrot. llvm-svn: 85271
* Remove unnecessary gotos to fall-thru successors.Sanjiv Gupta2009-10-272-1/+26
| | | | llvm-svn: 85257
* Test commit. Added '.' to the comment line.Johnny Chen2009-10-271-1/+1
| | | | llvm-svn: 85255
* apparently the X86 JIT isn't fully contextized, it is still using ↵Chris Lattner2009-10-271-0/+1
| | | | | | getGlobalContext() :( llvm-svn: 85252
* Correctly align double arguments in the stack.Rafael Espindola2009-10-271-0/+1
| | | | llvm-svn: 85235
* Now VFP instructions.Evan Cheng2009-10-271-57/+58
| | | | llvm-svn: 85186
* Change Thumb1 and Thumb2 instructions to separate opcode from operands with ↵Evan Cheng2009-10-272-227/+227
| | | | | | a tab instead of a space. llvm-svn: 85184
* Change ARM asm strings to separate opcode from operands with a tab instead ↵Evan Cheng2009-10-262-143/+143
| | | | | | of a space. llvm-svn: 85178
OpenPOWER on IntegriCloud