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* Switch the code added in r173885 to use the new, shiny RTTIChandler Carruth2013-01-312-9/+5
| | | | | | | | | | | | | | | | | | | | | | | infrastructure on MCStreamer to test for whether there is an MCELFStreamer object available. This is just a cleanup on the AsmPrinter side of things, moving ad-hoc tests of random APIs to a direct type query. But the AsmParser completely broken. There were no tests, it just blindly cast its streamer to an MCELFStreamer and started manipulating it. I don't have a test case -- this actually failed on LLVM's own regression test suite. Unfortunately the failure only appears when the stars, compilers, and runtime align to misbehave when we read a pointer to a formatted_raw_ostream as-if it were an MCAssembler. =/ UBSan would catch this immediately. Many thanks to Matt for doing about 80% of the debugging work here in GDB, Jim for helping to explain how exactly to fix this, and others for putting up with the hair pulling that ensued during debugging it. llvm-svn: 174118
* Give the MCStreamer class hierarchy LLVM RTTI facilities for use withChandler Carruth2013-01-311-6/+9
| | | | | | | | | | | | | | | | isa<> and dyn_cast<>. In several places, code is already hacking around the absence of this, and there seem to be several interfaces that might be lifted and/or devirtualized using this. This change was based on a discussion with Jim Grosbach about how best to handle testing for specific MCStreamer subclasses. He said that this was the correct end state, and everything else was too hacky so I decided to just make it so. No functionality should be changed here, this is just threading the kind through all the constructors and setting up the classof overloads. llvm-svn: 174113
* Update AMDGPURegisterInfo::eliminateFrameIndex() corresponding to r174083.NAKAMURA Takumi2013-01-312-0/+2
| | | | llvm-svn: 174106
* R600: Fold clamp, neg, absTom Stellard2013-01-311-3/+48
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174099
* R600: Consider bitcast when folding const_address node.Tom Stellard2013-01-312-0/+11
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174098
* R600: Make store_dummy intrinsic more general by passing export typeTom Stellard2013-01-312-4/+9
| | | | | | | Patch by: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 174097
* Remove unused variable, which should have been removed with r174083.Chad Rosier2013-01-311-1/+0
| | | | llvm-svn: 174094
* Update AArch64 backend to changed eliminateFrameIndex interface.Tim Northover2013-01-312-13/+10
| | | | llvm-svn: 174086
* [PEI] Pass the frame index operand number to the eliminateFrameIndex function.Chad Rosier2013-01-3122-170/+118
| | | | | | | Each target implementation was needlessly recomputing the index. Part of rdar://13076458 llvm-svn: 174083
* Add AArch64 as an experimental target.Tim Northover2013-01-3169-1/+22610
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for AArch64 (ARM's 64-bit architecture) to LLVM in the "experimental" category. Currently, it won't be built unless requested explicitly. This initial commit should have support for: + Assembly of all scalar (i.e. non-NEON, non-Crypto) instructions (except the late addition CRC instructions). + CodeGen features required for C++03 and C99. + Compilation for the "small" memory model: code+static data < 4GB. + Absolute and position-independent code. + GNU-style (i.e. "__thread") TLS. + Debugging information. The principal omission, currently, is performance tuning. This patch excludes the NEON support also reviewed due to an outbreak of batshit insanity in our legal department. That will be committed soon bringing the changes to precisely what has been approved. Further reviews would be gratefully received. llvm-svn: 174054
* Whitespace.Eric Christopher2013-01-311-9/+9
| | | | llvm-svn: 174009
* Check and allow floating point registers to select the size of theEric Christopher2013-01-311-2/+2
| | | | | | | register for inline asm. This conforms to how gcc allows for effective casting of inputs into gprs (fprs is already handled). llvm-svn: 174008
* PPC QPX requires a 32-byte aligned stackHal Finkel2013-01-302-1/+8
| | | | | | | On systems which support the QPX vector instructions, the stack must be 32-byte aligned. llvm-svn: 173993
* Restrict sin/cos optimization to 64-bit only for now. 32-bit is a bit messy ↵Evan Cheng2013-01-302-10/+14
| | | | | | and less critical. llvm-svn: 173987
* Initialize hasQPX in PPCSubtargetHal Finkel2013-01-301-0/+1
| | | | | | This should have gone in with r173973. llvm-svn: 173984
* Add definitions for the PPC a2q core marked as having QPX availableHal Finkel2013-01-302-0/+9
| | | | | | | | This is the first commit of a large series which will add support for the QPX vector instruction set to the PowerPC backend. This instruction set is used on the IBM Blue Gene/Q supercomputers. llvm-svn: 173973
* Add a special ARM trap encoding for NaCl.Eli Bendersky2013-01-308-6/+66
| | | | | | | | More details in this thread: http://lists.cs.uiuc.edu/pipermail/llvm-commits/Week-of-Mon-20130128/163783.html Patch by JF Bastien llvm-svn: 173943
* Add missing header and test cases for r173939.Logan Chien2013-01-301-0/+112
| | | | llvm-svn: 173941
* Override virtual function for ARM EH directives.Logan Chien2013-01-301-2/+216
| | | | llvm-svn: 173939
* Removing initializer for the field removed in r173887David Blaikie2013-01-301-1/+1
| | | | llvm-svn: 173888
* Remove unused variable (introduced in r173884) to clear clang -Werror buildDavid Blaikie2013-01-301-2/+0
| | | | llvm-svn: 173887
* Forgot to add new file to CMakeListsJack Carter2013-01-301-0/+1
| | | | llvm-svn: 173886
* This patch implements runtime ARM specificJack Carter2013-01-302-0/+21
| | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter llvm-svn: 173885
* This patch implements runtime Mips specificJack Carter2013-01-306-3/+113
| | | | | | | | setting of ELF header e_flags. Contributer: Jack Carter llvm-svn: 173884
* This patch reworks how llvm targets set Jack Carter2013-01-302-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | and update ELF header e_flags. Currently gathering information such as symbol, section and data is done by collecting it in an MCAssembler object. From MCAssembler and MCAsmLayout objects ELFObjectWriter::WriteObject() forms and streams out the ELF object file. This patch just adds a few members to the MCAssember class to store and access the e_flag settings. It allows for runtime additions to the e_flag by assembler directives. The standalone assembler can get to MCAssembler from getParser().getStreamer().getAssembler(). This patch is the generic infrastructure and will be followed by patches for ARM and Mips for their target specific use. Contributer: Jack Carter llvm-svn: 173882
* [mips] Lower EH_RETURN.Akira Hatanaka2013-01-3010-2/+184
| | | | | | Patch by Sasa Stankovic. llvm-svn: 173862
* Adding simple cast cost to ARMRenato Golin2013-01-292-2/+46
| | | | | | | | | | | Changing ARMBaseTargetMachine to return ARMTargetLowering intead of the generic one (similar to x86 code). Tests showing which instructions were added to cast when necessary or cost zero when not. Downcast to 16 bits are not lowered in NEON, so costs are not there yet. llvm-svn: 173849
* Use multiclass for post-increment store instructions.Jyotsna Verma2013-01-294-346/+125
| | | | llvm-svn: 173816
* Add constant extender support for MInst type instructions.Jyotsna Verma2013-01-292-75/+151
| | | | llvm-svn: 173813
* Remove dead code.Evan Cheng2013-01-291-10/+0
| | | | llvm-svn: 173812
* R600/AMDILPeepholeOptimizer.cpp: Tweak std::make_pair to satisfy C++11.NAKAMURA Takumi2013-01-291-1/+1
| | | | llvm-svn: 173807
* Fix typo in X86BaseInfo.h that I introduced in r157818.Hans Wennborg2013-01-291-2/+2
| | | | llvm-svn: 173798
* Fix 64-bit atomic operations in Thumb mode.Tim Northover2013-01-291-74/+46
| | | | | | | | The ARM and Thumb variants of LDREXD and STREXD have different constraints and take different operands. Previously the code expanding atomic operations didn't take this into account and asserted in Thumb mode. llvm-svn: 173780
* Merge SSE and AVX shuffle instructions in the comment printer.Craig Topper2013-01-291-98/+14
| | | | llvm-svn: 173777
* Teach SDISel to combine fsin / fcos into a fsincos node if the followingEvan Cheng2013-01-2910-15/+102
| | | | | | | | | | | | | | | | | | conditions are met: 1. They share the same operand and are in the same BB. 2. Both outputs are used. 3. The target has a native instruction that maps to ISD::FSINCOS node or the target provides a sincos library call. Implemented the generic optimization in sdisel and enabled it for Mac OSX. Also added an additional optimization for x86_64 Mac OSX by using an alternative entry point __sincos_stret which returns the two results in xmm0 / xmm1. rdar://13087969 PR13204 llvm-svn: 173755
* Add isBGQ method to PPCSubtargetHal Finkel2013-01-291-0/+2
| | | | | | This function will be used in future commits. llvm-svn: 173729
* Fix 256-bit PALIGNR comment decoding to understand that it works on ↵Craig Topper2013-01-281-2/+11
| | | | | | independent 256-bit lanes. llvm-svn: 173674
* Add missing break in 256-bit palignr comment printing. No test case yet ↵Craig Topper2013-01-281-0/+1
| | | | | | because the comment itself is still wrong. llvm-svn: 173669
* Fix inconsistent usage of PALIGN and PALIGNR when referring to the same ↵Craig Topper2013-01-287-34/+35
| | | | | | instruction. llvm-svn: 173667
* Remove addToNoHelperNeeded function that was left unused after r173649. ↵Craig Topper2013-01-281-6/+0
| | | | | | Fixes a -Wunused warning. llvm-svn: 173664
* Make some code a little simpler.Reed Kotler2013-01-282-40/+40
| | | | llvm-svn: 173649
* [XCore] Add missing l2rus instructions.Richard Osborne2013-01-272-1/+14
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 173634
* [XCore] Add missing l2r instructions.Richard Osborne2013-01-271-1/+12
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 173629
* [XCore] Add missing 1r instructions.Richard Osborne2013-01-271-6/+21
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 173624
* [XCore] Add missing 0r instructions.Richard Osborne2013-01-271-3/+44
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 173623
* Convert the CPP backend to use the AttributeSet instead of AttributeWithIndex.Bill Wendling2013-01-271-26/+37
| | | | | | Further removal of the introspective AttributeWithIndex thing. Also fix the #includes. llvm-svn: 173599
* X86: Decode PALIGN operands so I don't have to do it in my head.Benjamin Kramer2013-01-264-1/+36
| | | | llvm-svn: 173572
* X86: Do splat promotion later, so the optimizer can chew on it first.Benjamin Kramer2013-01-261-10/+10
| | | | | | | | | | | | This catches many cases where we can emit a more efficient shuffle for a specific mask or when the mask contains undefs. Once the splat is lowered to unpacks we can't do that anymore. There is a possibility of moving the promotion after pshufb matching, but I'm not sure if pshufb with a mask loaded from memory is faster than 3 shuffles, so I avoided that for now. llvm-svn: 173569
* fix use of std::std. it's ordered set.Reed Kotler2013-01-261-3/+3
| | | | llvm-svn: 173563
* Remove unused variables, silences -Wunused-variableDmitri Gribenko2013-01-251-4/+2
| | | | llvm-svn: 173526
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