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* Arm and thumb call instructions are also in different orders.Eric Christopher2010-12-211-13/+24
| | | | | | Fixes rdar://8782223 llvm-svn: 122313
* rename MVT::Flag to MVT::Glue. "Flag" is a terrible name forChris Lattner2010-12-2120-82/+82
| | | | | | | something that just glues two nodes together, even if it is sometimes used for flags. llvm-svn: 122310
* If we're not using reg+reg offset we're using reg+imm, set the opcodeEric Christopher2010-12-211-2/+2
| | | | | | | | | to be the one we want to use. bugpoint reduced testcase is a little large, I'll see if I can simplify it down more. Fixes part of rdar://8782207 llvm-svn: 122307
* Fix a copy-pasto. When the tBR_JTr instruction was converted to using theBill Wendling2010-12-211-1/+1
| | | | | | | | | tPseudoInst class, its size was changed from "special" to "2 bytes". This is incorrect because the jump table will no longer be taken into account when calculating branch offsets. <rdar://problem/8782216> llvm-svn: 122303
* Comment cleanups.Bill Wendling2010-12-211-2/+2
| | | | llvm-svn: 122302
* Implement feedback from Bruno on making pblendvb an x86-specific ISD node in ↵Nate Begeman2010-12-204-11/+14
| | | | | | | | addition to being an intrinsic, and convert lowering to use it. Hopefully the pattern fragment is doing the right thing with XMM0, looks correct in testing. llvm-svn: 122277
* Teach the MBlaze disassembler to disassemble special purpose registers.Wesley Peck2010-12-202-8/+11
| | | | llvm-svn: 122269
* Teach the MBlaze asm parser how to parse special purpose register names.Wesley Peck2010-12-204-38/+134
| | | | llvm-svn: 122261
* Add header...Daniel Dunbar2010-12-201-0/+1
| | | | llvm-svn: 122247
* X86/MC/Mach-O: Split out createX86MachObjectWriter().Daniel Dunbar2010-12-204-17/+48
| | | | llvm-svn: 122246
* now that addc/adde are gone, "ADDC" in the X86 backend uses EFLAGS results,Chris Lattner2010-12-201-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | the same as setcc. Optimize ADDC(0,0,FLAGS) -> SET_CARRY(FLAGS). This is a step towards finishing off PR5443. In the testcase in that bug we now get: movq %rdi, %rax addq %rsi, %rax sbbq %rcx, %rcx testb $1, %cl setne %dl ret instead of: movq %rdi, %rax addq %rsi, %rax movl $0, %ecx adcq $0, %rcx testq %rcx, %rcx setne %dl ret llvm-svn: 122219
* We lower setb to sbb with the hope that the and will go away, when it Chris Lattner2010-12-201-0/+6
| | | | | | | | | | | | | | | | | | | | | doesn't, match it back to setb. On a 64-bit version of the testcase before we'd get: movq %rdi, %rax addq %rsi, %rax sbbb %dl, %dl andb $1, %dl ret now we get: movq %rdi, %rax addq %rsi, %rax setb %dl ret llvm-svn: 122217
* use for loop over types.Chris Lattner2010-12-201-20/+6
| | | | llvm-svn: 122214
* Change the X86 backend to stop using the evil ADDC/ADDE/SUBC/SUBE nodes (whichChris Lattner2010-12-204-42/+173
| | | | | | | | | | | | | their carry depenedencies with MVT::Flag operands) and use clean and beautiful EFLAGS dependences instead. We do this by changing the modelling of SBB/ADC to have EFLAGS input and outputs (which is what requires the previous scheduler change) and change X86 ISelLowering to custom lower ADDC and friends down to X86ISD::ADD/ADC/SUB/SBB nodes. With the previous series of changes, this causes no changes in the testsuite, woo. llvm-svn: 122213
* Prevents PerformShuffleCombine from creating a node with an illegal type ↵Mon P Wang2010-12-191-2/+7
| | | | | | | | after legalize types has run, e.g., prevent creating an i64 node from a v2i64 when i64 is not a legal type. llvm-svn: 122206
* improve the setcc -> setcc_carry optimization to happen moreChris Lattner2010-12-193-12/+34
| | | | | | | | consistently by moving it out of lowering into dag combine. Add some missing patterns for matching away extended versions of setcc_c. llvm-svn: 122201
* simplify some code to just reuse a setcc if we can instead of Chris Lattner2010-12-191-11/+16
| | | | | | going through the CSE maps to get it. llvm-svn: 122196
* Add missing standard headers. Patch by Joerg Sonnenberger!Nick Lewycky2010-12-192-0/+2
| | | | llvm-svn: 122193
* Add missing std:: prefixes to some calls. C++ doesn't require that <cfoo>Nick Lewycky2010-12-192-2/+2
| | | | | | | headers provide symbols outside namespace std and the LLVM coding standards state that we should prefix all of them. llvm-svn: 122192
* now that generic vector types aren't selected onto MMX operations,Chris Lattner2010-12-191-8/+4
| | | | | | we don't need -disable-mmx anymore. llvm-svn: 122189
* reduce copy/paste programming with the power of for loops.Chris Lattner2010-12-191-40/+25
| | | | llvm-svn: 122187
* X86 supports i8/i16 overflow ops (except i8 multiplies), we shouldChris Lattner2010-12-191-17/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | generate them. Now we compile: define zeroext i8 @X(i8 signext %a, i8 signext %b) nounwind ssp { entry: %0 = tail call %0 @llvm.sadd.with.overflow.i8(i8 %a, i8 %b) %cmp = extractvalue %0 %0, 1 br i1 %cmp, label %if.then, label %if.end into: _X: ## @X ## BB#0: ## %entry subl $12, %esp movb 16(%esp), %al addb 20(%esp), %al jo LBB0_2 Before we were generating: _X: ## @X ## BB#0: ## %entry pushl %ebp movl %esp, %ebp subl $8, %esp movb 12(%ebp), %al testb %al, %al setge %cl movb 8(%ebp), %dl testb %dl, %dl setge %ah cmpb %cl, %ah sete %cl addb %al, %dl testb %dl, %dl setge %al cmpb %al, %ah setne %al andb %cl, %al testb %al, %al jne LBB0_2 llvm-svn: 122186
* recognize an unsigned add with overflow idiom into uadd.Chris Lattner2010-12-191-20/+1
| | | | | | | | | | | | | | | | | | | | | | | | | This resolves a README entry and technically resolves PR4916, but we still get poor code for the testcase in that PR because GVN isn't CSE'ing uadd with add, filed as PR8817. Previously we got: _test7: ## @test7 addq %rsi, %rdi cmpq %rdi, %rsi movl $42, %eax cmovaq %rsi, %rax ret Now we get: _test7: ## @test7 addq %rsi, %rdi movl $42, %eax cmovbq %rsi, %rax ret llvm-svn: 122182
* Restore the behavior of frame lowering before my refactoring.Anton Korobeynikov2010-12-184-12/+29
| | | | | | | | It turns out that ppc backend has really weird interdependencies over different hooks and all stuff is fragile wrt small changes. This should fix PR8749 llvm-svn: 122155
* Remove the MCObjectFormat class.Rafael Espindola2010-12-184-44/+0
| | | | llvm-svn: 122147
* Move some data to the TargetWriter.Rafael Espindola2010-12-183-22/+19
| | | | llvm-svn: 122134
* r120333 changed the opcode for the Thumb1 stuff from ARM::tMOVr toBill Wendling2010-12-181-1/+1
| | | | | | | | | | | ARM::tMOVgpr2gpr. But this check didn't change. As a result, we were getting misaligned references to the jump table from an ADR instruction. There is a test case, but unfortunately it's sensitive to random code changes. <rdar://problem/8782223> llvm-svn: 122131
* RemoveUnusedCPEntries can change things. Track it.Bill Wendling2010-12-181-1/+1
| | | | llvm-svn: 122129
* Relax push instructions.Rafael Espindola2010-12-181-0/+3
| | | | llvm-svn: 122121
* Rearrange some Neon multiclasses. No functional changes.Bob Wilson2010-12-181-74/+76
| | | | llvm-svn: 122119
* Fix result type of Neon floating-point comparisons against zero.Bob Wilson2010-12-181-2/+2
| | | | | | The result vector elements are always integers. Radar 8782191. llvm-svn: 122112
* Add some missing entries in ARMTargetLowering::getTargetNodeName.Bob Wilson2010-12-181-0/+5
| | | | llvm-svn: 122111
* During local stack slot allocation, the materializeFrameBaseRegister functionBill Wendling2010-12-172-8/+14
| | | | | | | | | | | | | | | may be called. If the entry block is empty, the insertion point iterator will be the "end()" value. Calling ->getParent() on it (among others) causes problems. Modify materializeFrameBaseRegister to take the machine basic block and insert the frame base register at the beginning of that block. (It's very similar to what the code does all ready. The only difference is that it will always insert at the beginning of the entry block instead of after a previous materialization of the frame base register. I doubt that that matters here.) <rdar://problem/8782198> llvm-svn: 122104
* Avoid report_fatal_error in ARM's PrintAsmOperand method.Bob Wilson2010-12-171-1/+1
| | | | | | | The standard error handling in AsmPrinter::EmitInlineAsm handles this much better, so just use it. llvm-svn: 122100
* Add support for matching psign & plendvb to the x86 targetNate Begeman2010-12-174-41/+160
| | | | | | Remove unnecessary pandn patterns, 'vnot' patfrag looks through bitcasts llvm-svn: 122098
* If The ARM WriteNopData() gets an unaligned byte count to pad out, fill in withJim Grosbach2010-12-171-5/+13
| | | | | | a partial value. rdar://8782954 llvm-svn: 122078
* Add bits 31-28 to the Thumb2 encoding of TBB/TBH.Jim Grosbach2010-12-171-2/+2
| | | | llvm-svn: 122076
* Handle 2 and 4 byte data blob fixup values for ARM.Jim Grosbach2010-12-171-0/+4
| | | | llvm-svn: 122075
* Pass StringRefs by value, for consistency.Benjamin Kramer2010-12-171-1/+1
| | | | llvm-svn: 122074
* Stub out explicit MCELFObjectTargetWriter interface.Rafael Espindola2010-12-173-4/+22
| | | | llvm-svn: 122067
* Move createELFObjectWriter to its own header.Rafael Espindola2010-12-173-0/+3
| | | | llvm-svn: 122064
* Don't feed 19 bit immediates to ILA.Kalle Raiskila2010-12-171-3/+3
| | | | | | Patch (slightly modified) by Visa Putkinen. llvm-svn: 122052
* MC/ARM: Use aggressive symbol folding (important for jump tables, for example).Daniel Dunbar2010-12-171-1/+2
| | | | llvm-svn: 122044
* MC/Mach-O: On second thought, use a custom hook for enabling aggressiveDaniel Dunbar2010-12-171-1/+2
| | | | | | | | | | IsSymbolRefDifferenceFullyResolved, it turns out this does change behavior on enough cases for x86-32 that I would rather wait a bit on it. - In practice, we will want to change this eventually because it only means we generate less relocations (it also eliminates the need for the horrible '.set' hack that Darwin requires in some places). llvm-svn: 122042
* MC/Target: Remove HasScatteredSymbols target hook variable, which has beenDaniel Dunbar2010-12-174-17/+5
| | | | | | superceded and was effectively dead. llvm-svn: 122024
* Use PairDRegs to implement ConcatVectors. No functionality change.Bob Wilson2010-12-171-7/+1
| | | | llvm-svn: 122017
* Make pushq produce signed relocations.Rafael Espindola2010-12-161-1/+4
| | | | llvm-svn: 122005
* Fix MBlaze backend call instructions so that arguments passed through registersWesley Peck2010-12-162-10/+11
| | | | | | | are correctly marked as used. This removes a hack where the call instructions marked all possible argument registers as used in the tablegen description. llvm-svn: 121994
* Pseudo-ize the Thumb1 tBfar pattern. rdar://8777974Jim Grosbach2010-12-162-3/+12
| | | | llvm-svn: 121990
* MC/Mach-O: Lift some MachObjectWriter arguments into the target specificDaniel Dunbar2010-12-163-20/+33
| | | | | | interface. llvm-svn: 121981
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