summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* Scalar f32/f64 are also subregs of ymm regsNate Begeman2010-12-031-0/+6
| | | | llvm-svn: 120844
* Remove SSE1-4 disable when AVX is enabled. While this may be useful for ↵Nate Begeman2010-12-031-12/+7
| | | | | | | | development, it completely breaks scalar fp in xmm regs when AVX is enabled. llvm-svn: 120843
* When using the 'push' mnemonic for Thumb2 stmdb, be explicit when it's theJim Grosbach2010-12-031-0/+4
| | | | | | 32-bit wide version by adding the .w suffix. llvm-svn: 120838
* Remove unused variable.Benjamin Kramer2010-12-031-1/+0
| | | | llvm-svn: 120836
* Reduce t2 ldr/str instructions to the correct t1 versions when there's anJim Grosbach2010-12-031-6/+6
| | | | | | immediate offset. llvm-svn: 120833
* fix ARM::fixup_arm_branch, cleanup, and share more code between ELF and DarwinJason W Kim2010-12-031-23/+10
| | | | llvm-svn: 120832
* No need to declare EncoderMethod property anymore; just assign to it.Jim Grosbach2010-12-031-3/+3
| | | | llvm-svn: 120831
* Add FIXMEs.Jim Grosbach2010-12-031-0/+2
| | | | llvm-svn: 120824
* Size reduction for tPUSH come from t2STMDB_UPD, not t2STMIA_UPD.Jim Grosbach2010-12-031-1/+2
| | | | llvm-svn: 120822
* Don't overwrite the opcode passed into the T1Special pattern.Bill Wendling2010-12-031-4/+5
| | | | llvm-svn: 120782
* Add Thumb encoding for some more instructions.Bill Wendling2010-12-031-19/+68
| | | | llvm-svn: 120780
* Try to resolve symbol differences early, and if successful create a plainRafael Espindola2010-12-031-0/+10
| | | | | | | data fragment. This reduces the time to assemble the test in 8711 from 60s to 54s. llvm-svn: 120767
* The tLDR instruction wasn't encoded properly:Bill Wendling2010-12-031-2/+6
| | | | | | | | | <MCInst 2251 <MCOperand Reg:70> <MCOperand Reg:66> <MCOperand Imm:0> <MCOperand Reg:0> <MCOperand Imm:14> <MCOperand Reg:0>> Notice that the "reg" here is 0, which is an invalid register. Put a check in the code for this to prevent crashing. llvm-svn: 120766
* Trailing whitespace.Jim Grosbach2010-12-021-32/+32
| | | | llvm-svn: 120748
* Use set directive for StartMinusEndExpr.Devang Patel2010-12-021-2/+3
| | | | | | This is a fix for llvm-gcc-i386-darwin9 buildbot failure. llvm-svn: 120742
* When expanding the MOVCCi32imm, make sure to use the ARM movt/movw opcodes,Jim Grosbach2010-12-021-4/+5
| | | | | | not thumb2. llvm-svn: 120711
* Fix copy/pasto in vmin.f32 encoding.Jim Grosbach2010-12-021-1/+1
| | | | llvm-svn: 120709
* Teaching MBlaze backend how to reverse branch conditions.Wesley Peck2010-12-022-0/+35
| | | | llvm-svn: 120707
* Add support for binary encoding of ARM 'adr' instructions referencing constantJim Grosbach2010-12-025-38/+56
| | | | | | pool entries (LEApcrel pseudo). Ongoing saga of rdar://8542291. llvm-svn: 120635
* Revert r120580.Devang Patel2010-12-021-14/+0
| | | | llvm-svn: 120630
* Fix and re-enable tail call optimization of expanded libcalls.Evan Cheng2010-12-012-19/+23
| | | | llvm-svn: 120622
* fixing style nit: move class static to global staticJason W Kim2010-12-011-42/+41
| | | | llvm-svn: 120619
* Add a post encoder method to the VFP instructions to convert them to the Thumb2Bill Wendling2010-12-013-4/+22
| | | | | | encoding if we're in that mode. llvm-svn: 120608
* Use the correct fixup type for ARM VLDR*Jim Grosbach2010-12-011-2/+2
| | | | llvm-svn: 120604
* Refactor LEApcrelJT as a pseudo-instructionlowered to a cannonical ADRJim Grosbach2010-12-014-16/+72
| | | | | | | instruction at MC lowering. Add binary encoding information for the ADR, including fixup data for the label operand. llvm-svn: 120594
* Add correct encodings for STRD and LDRD, including fixup support. ↵Owen Anderson2010-12-017-32/+74
| | | | | | Additionally, update these to unified syntax. llvm-svn: 120589
* kill trailing spaceJason W Kim2010-12-011-1/+1
| | | | llvm-svn: 120586
* 10 bits, not 12.Jim Grosbach2010-12-013-6/+6
| | | | llvm-svn: 120584
* Disable debug info for x86-darwin9 and earlier until PR 8715 and radar ↵Devang Patel2010-12-011-0/+14
| | | | | | 8709290 are fixed. llvm-svn: 120580
* I don't think it makes any sense to assert that the target supports SSE3 here.Duncan Sands2010-12-011-4/+0
| | | | | | | | | | The user (i.e. whoever generated a call to the intrinsic in the first place) is essentially asking for a particular instruction to be placed in the assembler. If that instruction won't execute on the target machine, that's their problem not ours. Two buildbots with processors that don't support SSE3 were barfing on the apm.ll test in CodeGen/X86 because of this assertion. llvm-svn: 120574
* ptx: bug fix: use after freeChe-Liang Chiou2010-12-011-7/+8
| | | | llvm-svn: 120571
* Elaborate on FIXME.Jim Grosbach2010-12-011-1/+4
| | | | llvm-svn: 120552
* Move the ARMAsmPrinter class defintiion into a header file.Jim Grosbach2010-12-014-100/+127
| | | | llvm-svn: 120551
* Speculatively disable x86 portion of r120501 to appease the x86_64 buildbot.Evan Cheng2010-12-011-0/+2
| | | | llvm-svn: 120549
* Remove "comparison of integers of different signs" warning by making theBill Wendling2010-12-011-1/+1
| | | | | | variable unsigned. llvm-svn: 120541
* General cleanups of comments.Bill Wendling2010-12-011-11/+7
| | | | llvm-svn: 120536
* ARM/MC/ELF relocation "hello world" for movw/movt.Jason W Kim2010-12-011-44/+75
| | | | | | | | | | | Lifted adjustFixupValue() from Darwin for sharing w ELF. Test added TODO: refactor ELFObjectWriter::RecordRelocation more. Possibly share more code with Darwin? Lots more relocations... llvm-svn: 120534
* Formatting. It's all the rage!Bill Wendling2010-12-011-35/+37
| | | | llvm-svn: 120533
* More refactoring. This time the T1pI pattern.Bill Wendling2010-12-011-131/+96
| | | | llvm-svn: 120532
* Refactor load/store handling again. Simplify and make some room forEric Christopher2010-12-011-103/+60
| | | | | | reg+reg handling. llvm-svn: 120526
* Initialize an ARMConstantPoolValue field.Jan Wen Voung2010-12-011-1/+1
| | | | llvm-svn: 120525
* s/T1pIEncode/T1pILdStEncode/gBill Wendling2010-12-012-62/+62
| | | | | | s/T1pIEncodeImm/T1pILdStEncodeImm/g llvm-svn: 120524
* Renaming variables to coincide with documentation. No functionality change.Bill Wendling2010-12-012-21/+21
| | | | llvm-svn: 120522
* Refactor T1sI and T1sIt encodings into helper classes.Bill Wendling2010-12-011-93/+78
| | | | llvm-svn: 120518
* Refactor the T1sIt encodings into a parent class to get rid of all of the "let"Bill Wendling2010-12-011-131/+85
| | | | | | statements. llvm-svn: 120512
* Use by-name rather than by-order matching for NEON operands.Owen Anderson2010-12-011-318/+318
| | | | llvm-svn: 120507
* Enable sibling call optimization of libcalls which are expanded duringEvan Cheng2010-11-307-62/+112
| | | | | | | | | | | legalization time. Since at legalization time there is no mapping from SDNode back to the corresponding LLVM instruction and the return SDNode is target specific, this requires a target hook to check for eligibility. Only x86 and ARM support this form of sibcall optimization right now. rdar://8707777 llvm-svn: 120501
* Rename operands to match ARM documentation. No functionality change.Bill Wendling2010-11-302-101/+105
| | | | llvm-svn: 120500
* Fix typo.Jim Grosbach2010-11-301-1/+1
| | | | llvm-svn: 120499
* Trailing whitespace.Jim Grosbach2010-11-301-3/+3
| | | | llvm-svn: 120497
OpenPOWER on IntegriCloud