summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* VLDR fixups need special handling under Thumb. While the encoding is the same,Owen Anderson2010-12-083-2/+23
| | | | | | the order of the bytes in the data stream is flipped around. llvm-svn: 121215
* Fix a warning about a variable which is only used in an assertion.Matt Beaumont-Gay2010-12-071-2/+2
| | | | llvm-svn: 121206
* Cleanup in the Darwin end. No functionality change.Bill Wendling2010-12-071-5/+7
| | | | llvm-svn: 121198
* Fix a bad prologue / epilogue codegen bug where the compiler would emit illegalEvan Cheng2010-12-072-68/+92
| | | | | | | | | | | vpush instructions to save / restore VFP / NEON registers like this: vpush {d8,d10,d11} vpop {d8,d10,d11} vpush and vpop do not allow gaps in the register list. rdar://8728956 llvm-svn: 121197
* A bit of cleanup: early exit ApplyFixup and cache the Fixup offset. NoBill Wendling2010-12-071-13/+14
| | | | | | functionality change. llvm-svn: 121195
* Binary encoding for ARM tLDRspi and tSTRspi.Jim Grosbach2010-12-073-8/+42
| | | | llvm-svn: 121186
* Fix Thumb2 encoding of the S bit.Owen Anderson2010-12-072-23/+4
| | | | llvm-svn: 121182
* Refactor the ARM CMPz* patterns to just use the normal CMP instructions whenJim Grosbach2010-12-076-41/+25
| | | | | | | possible. They were duplicates for everything exception the source pattern before. llvm-svn: 121179
* Code clean up; no functionality change.Evan Cheng2010-12-071-16/+14
| | | | llvm-svn: 121176
* Code clean up; no functionality change.Evan Cheng2010-12-071-11/+8
| | | | llvm-svn: 121172
* Remove target specific node MipsISD::CMov, which is not used because all ↵Bruno Cardoso Lopes2010-12-073-9/+1
| | | | | | conditional moves are directly matched using tablegen patterns. If there's a need in the future, we can introduce it again llvm-svn: 121164
* Match a pattern generated by a dag combiner opt where:Bruno Cardoso Lopes2010-12-072-2/+12
| | | | | | | | (select (load (load tga0)) (load tga1)) => (load (select (load tga0) tga1)) Thanks to Akira for pointing that. llvm-svn: 121163
* Encode the literal field for tCMPzi instruction.Jim Grosbach2010-12-071-1/+2
| | | | llvm-svn: 121153
* Add parens to pacify gcc.Benjamin Kramer2010-12-071-1/+1
| | | | llvm-svn: 121142
* PR5207: Change APInt methods trunc(), sext(), zext(), sextOrTrunc() andJay Foad2010-12-071-1/+1
| | | | | | | | zextOrTrunc(), and APSInt methods extend(), extOrTrunc() and new method trunc(), to be const and to return a new value instead of modifying the object in place. llvm-svn: 121120
* lib/Target/X86/X86MCAsmInfo.cpp: [PR8741] On Win64, specify explicit ↵NAKAMURA Takumi2010-12-071-1/+3
| | | | | | | | PrivateGlobalPrefix as ".L". Or, global symbols @Lxxxx might be treated as temporal symbol by MCSymbol. llvm-svn: 121103
* Second attempt at converting Thumb2's LDRpci, including updating the ↵Owen Anderson2010-12-078-72/+101
| | | | | | gazillion places that need to know about it. llvm-svn: 121082
* Add fixup for Thumb1 BL/BLX instructions.Jim Grosbach2010-12-065-17/+78
| | | | llvm-svn: 121072
* Adding bug fix that was suppose to be part of 121044.Wesley Peck2010-12-061-6/+6
| | | | | | patch contributed by Jack Whitham! llvm-svn: 121049
* Fixed reversed operands for IDIV and CMP instructions in MBlaze backend.Wesley Peck2010-12-061-24/+24
| | | | | | | | Use BRAD instead of BRD for indirect branches in MBlaze backend. patch contributed by Jack Whitham! llvm-svn: 121044
* Fix a 16-bit immediate value detection bug in the MBlaze delay slot filler.Wesley Peck2010-12-061-48/+86
| | | | | | | | Address more hazards in the MBlaze delay slot filler. patch contributed by Jack Whitham! llvm-svn: 121037
* Remove the instruction fragment to data fragment lowering since it was causingRafael Espindola2010-12-064-18/+18
| | | | | | freed data to be read. I will open a bug to track it being reenabled. llvm-svn: 121028
* Revert r121021, which broke the buildbots.Owen Anderson2010-12-062-34/+20
| | | | llvm-svn: 121026
* Trailing whitespace.Jim Grosbach2010-12-061-1/+1
| | | | llvm-svn: 121024
* Improve handling of Thumb2 PC-relative loads by converting LDRpci (and ↵Owen Anderson2010-12-062-20/+34
| | | | | | friends) to Pseudos. llvm-svn: 121021
* Encode the register operand of ARM CondCode operands correctly. ARM::CPSR ifJim Grosbach2010-12-061-2/+2
| | | | | | the instruction is predicated, reg0 otherwise. llvm-svn: 121020
* The ARM AsmMatcher needs to know that the CCOut operand is a register value,Jim Grosbach2010-12-062-1/+27
| | | | | | not an immediate. It stores either ARM::CPSR or reg0. llvm-svn: 121018
* Second try at making direct object emission produce the same resultsRafael Espindola2010-12-062-7/+0
| | | | | | | as llc + llvm-mc. This time ELF is not changed and I tested that llvm-gcc bootstrap on darwin10 using darwin9's assembler and linker. llvm-svn: 121006
* ptx: add shift instructionsChe-Liang Chiou2010-12-061-0/+27
| | | | llvm-svn: 120982
* Eliminate unneeded #include's.Evan Cheng2010-12-051-2/+0
| | | | llvm-svn: 120971
* ARM/CMakeLists.txt: Add missing MLxExpansionPass.cpp since r120960.NAKAMURA Takumi2010-12-051-0/+1
| | | | llvm-svn: 120966
* Code clean up.Evan Cheng2010-12-051-6/+6
| | | | llvm-svn: 120965
* Remove an unused variable.Evan Cheng2010-12-051-2/+1
| | | | llvm-svn: 120964
* Making use of VFP / NEON floating point multiply-accumulate / subtraction isEvan Cheng2010-12-0519-191/+771
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | difficult on current ARM implementations for a few reasons. 1. Even though a single vmla has latency that is one cycle shorter than a pair of vmul + vadd, a RAW hazard during the first (4? on Cortex-a8) can cause additional pipeline stall. So it's frequently better to single codegen vmul + vadd. 2. A vmla folowed by a vmul, vmadd, or vsub causes the second fp instruction to stall for 4 cycles. We need to schedule them apart. 3. A vmla followed vmla is a special case. Obvious issuing back to back RAW vmla + vmla is very bad. But this isn't ideal either: vmul vadd vmla Instead, we want to expand the second vmla: vmla vmul vadd Even with the 4 cycle vmul stall, the second sequence is still 2 cycles faster. Up to now, isel simply avoid codegen'ing fp vmla / vmls. This works well enough but it isn't the optimial solution. This patch attempts to make it possible to use vmla / vmls in cases where it is profitable. A. Add missing isel predicates which cause vmla to be codegen'ed. B. Make sure the fmul in (fadd (fmul)) has a single use. We don't want to compute a fmul and a fmla. C. Add additional isel checks for vmla, avoid cases where vmla is feeding into fp instructions (except for the #3 exceptional case). D. Add ARM hazard recognizer to model the vmla / vmls hazards. E. Add a special pre-regalloc case to expand vmla / vmls when it's likely the vmla / vmls will trigger one of the special hazards. Work in progress, only A+B are enabled. llvm-svn: 120960
* Teach X86ISelLowering that the second result of X86ISD::UMUL is a flagsChris Lattner2010-12-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | result. This allows us to compile: void *test12(long count) { return new int[count]; } into: test12: movl $4, %ecx movq %rdi, %rax mulq %rcx movq $-1, %rdi cmovnoq %rax, %rdi jmp __Znam ## TAILCALL instead of: test12: movl $4, %ecx movq %rdi, %rax mulq %rcx seto %cl testb %cl, %cl movq $-1, %rdi cmoveq %rax, %rdi jmp __Znam Of course it would be even better if the regalloc inverted the cmov to 'cmovoq', which would eliminate the need for the 'movq %rdi, %rax'. llvm-svn: 120936
* it turns out that when ".with.overflow" intrinsics were added to the X86Chris Lattner2010-12-055-20/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | backend that they were all implemented except umul. This one fell back to the default implementation that did a hi/lo multiply and compared the top. Fix this to check the overflow flag that the 'mul' instruction sets, so we can avoid an explicit test. Now we compile: void *func(long count) { return new int[count]; } into: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] seto %cl ## encoding: [0x0f,0x90,0xc1] testb %cl, %cl ## encoding: [0x84,0xc9] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL instead of: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL Other than the silly seto+test, this is using the o bit directly, so it's going in the right direction. llvm-svn: 120935
* generalize the previous check to handle -1 on either side of the Chris Lattner2010-12-051-7/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | select, inserting a not to compensate. Add a missing isZero check that I lost somehow. This improves codegen of: void *func(long count) { return new int[count]; } from: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] testq %rdx, %rdx ## encoding: [0x48,0x85,0xd2] movq $-1, %rdi ## encoding: [0x48,0xc7,0xc7,0xff,0xff,0xff,0xff] cmoveq %rax, %rdi ## encoding: [0x48,0x0f,0x44,0xf8] jmp __Znam ## TAILCALL ## encoding: [0xeb,A] to: __Z4funcl: ## @_Z4funcl movl $4, %ecx ## encoding: [0xb9,0x04,0x00,0x00,0x00] movq %rdi, %rax ## encoding: [0x48,0x89,0xf8] mulq %rcx ## encoding: [0x48,0xf7,0xe1] cmpq $1, %rdx ## encoding: [0x48,0x83,0xfa,0x01] sbbq %rdi, %rdi ## encoding: [0x48,0x19,0xff] notq %rdi ## encoding: [0x48,0xf7,0xd7] orq %rax, %rdi ## encoding: [0x48,0x09,0xc7] jmp __Znam ## TAILCALL ## encoding: [0xeb,A] llvm-svn: 120932
* Improve an integer select optimization in two ways:Chris Lattner2010-12-051-21/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | 1. generalize (select (x == 0), -1, 0) -> (sign_bit (x - 1)) to: (select (x == 0), -1, y) -> (sign_bit (x - 1)) | y 2. Handle the identical pattern that happens with !=: (select (x != 0), y, -1) -> (sign_bit (x - 1)) | y cmov is often high latency and can't fold immediates or memory operands. For example for (x == 0) ? -1 : 1, before we got: < testb %sil, %sil < movl $-1, %ecx < movl $1, %eax < cmovel %ecx, %eax now we get: > cmpb $1, %sil > sbbl %eax, %eax > orl $1, %eax llvm-svn: 120929
* Initialize HasPOPCNT.Bill Wendling2010-12-041-1/+2
| | | | llvm-svn: 120923
* Add patterns for the x86 popcnt instruction.Benjamin Kramer2010-12-044-15/+32
| | | | | | | - Also adds a new POPCNT subtarget feature that is currently enabled if the target supports SSE4.2 (nehalem) or SSE4A (barcelona). llvm-svn: 120917
* Simplify code. No functionality change.Benjamin Kramer2010-12-041-4/+3
| | | | llvm-svn: 120907
* The Thumb tADDrSPi instruction is not valid when the destination is SP.Bob Wilson2010-12-041-1/+8
| | | | | | Check for that and try narrowing it to tADDspi instead. Radar 8724703. llvm-svn: 120892
* There are two reasons why we might want to useRafael Espindola2010-12-043-3/+10
| | | | | | | | | | | | | | | | foo = a - b .long foo instead of just .long a - b First, on darwin9 64 bits the assembler produces the wrong result. Second, if "a" is the end of the section all darwin assemblers (9, 10 and mc) will not consider a - b to be a constant but will if the dummy foo is created. Split how we handle these cases. The first one is something MC should take care of. The second one has to be handled by the caller. llvm-svn: 120889
* Encode condition code for Thumb1 conditional branch instruction.Jim Grosbach2010-12-041-3/+6
| | | | llvm-svn: 120865
* Correctly size-reduce the t2CMPzrr instruction to tCMPzr when possible.Jim Grosbach2010-12-031-1/+13
| | | | | | | tCMPzhir has undefined behavior when both source registers are low registers. rdar://8728577 llvm-svn: 120858
* Use correct variable names to match the patterns.Bill Wendling2010-12-031-13/+14
| | | | llvm-svn: 120857
* Match pattern operand names to expected encoding field names. This corrects theJim Grosbach2010-12-031-2/+2
| | | | | | operand encoding ordering of the instruction. llvm-svn: 120852
* Remove incorrect BL target encoding (it's similar to, but not the same as theJim Grosbach2010-12-031-16/+14
| | | | | | ARM instruction). Add encoding of bits 13 and 11. llvm-svn: 120849
* Encode the 32-bit wide Thumb (and Thumb2) instructions with the high orderJim Grosbach2010-12-031-1/+9
| | | | | | halfword being emitted to the stream first. rdar://8728174 llvm-svn: 120848
* Revert this change since it breaks a couple of the AVX tests.Nate Begeman2010-12-031-7/+12
| | | | | | I'm unclear if the tests are actually correct or not, but reverting for now. llvm-svn: 120847
OpenPOWER on IntegriCloud