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* Make pseudos FEXT_CCRX16_ins and FEXT_CCRXI16_ins into custom emitters.Reed Kotler2013-02-255-69/+70
| | | | llvm-svn: 176007
* Make psuedo FEXT_T8I816_ins into a custom emitter.Reed Kotler2013-02-245-61/+39
| | | | llvm-svn: 176002
* Fix PR14364.Bill Schmidt2013-02-244-20/+27
| | | | | | | | | | | This removes a const_cast hack from PPCRegisterInfo::hasReservedSpillSlot(). The proper place to save the frame index for the CR spill slot is in the PPCFunctionInfo object, not the PPCRegisterInfo object. No new test cases, as this just reimplements existing function. Existing tests such as test/CodeGen/PowerPC/crsave.ll are sufficient. llvm-svn: 175998
* TypoFrancois Pichet2013-02-241-1/+1
| | | | llvm-svn: 175991
* Revert r169638 because it broke Mesa llvmpipe tests.Nadav Rotem2013-02-241-6/+1
| | | | | | Fix PR15239. llvm-svn: 175985
* Make psuedo FEXT_T8I816_ins a custom inserter. It should be expandedReed Kotler2013-02-244-22/+34
| | | | | | as early as possible; which means during instruction selection. llvm-svn: 175984
* Add new base instruction def for cmpi, cmp, slt and sltu so that def/usesReed Kotler2013-02-231-5/+10
| | | | | | proper. Fixed this already a few days ago for slti. llvm-svn: 175975
* X86: Disable cmov-memory patterns on subtargets without cmov.Benjamin Kramer2013-02-231-6/+8
| | | | | | Fixes PR15115. llvm-svn: 175962
* Expand pseudos/macros for Selt. This is the last of the complexReed Kotler2013-02-233-0/+82
| | | | | | macros.The rest is some small misc. stuff. llvm-svn: 175950
* ARM: Convenience aliases for 'srs*' instructions.Jim Grosbach2013-02-233-0/+28
| | | | | | | | Handle an implied 'sp' operand. rdar://11466783 llvm-svn: 175940
* [mips] Emit call16 operator instead of got_disp. The former allows lazy binding.Akira Hatanaka2013-02-221-3/+1
| | | | llvm-svn: 175920
* x86_64: designate most general purpose and SSE registers as callee save ↵Peter Collingbourne2013-02-222-21/+28
| | | | | | under coldcc llvm-svn: 175911
* R600/SI: Add pattern for sign extension of i1 to i32.Michel Danzer2013-02-221-0/+5
| | | | | | | | | 16 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175887
* R600/SI: Add pattern for logical or of i1 values.Michel Danzer2013-02-221-0/+4
| | | | | | | | | 24 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175886
* R600/SI: Add pattern for fceil.Michel Danzer2013-02-221-1/+3
| | | | | | | | | 9 more little piglits with radeonsi. NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175885
* Make ARMAsmPrinter generate the correct alignment specifier syntax in ↵Kristof Beyls2013-02-221-2/+1
| | | | | | | | | instructions. The Printer will now print instructions with the correct alignment specifier syntax, like vld1.8 {d16}, [r0:64] llvm-svn: 175884
* Fix a nomenclature mistake. Slt->Slti in the functions. The "i" refersReed Kotler2013-02-222-8/+8
| | | | | | to the immediate operand of sli or cmp function. llvm-svn: 175865
* Expand mips16 SelT form pseudso/macros.Reed Kotler2013-02-223-0/+81
| | | | llvm-svn: 175862
* Remove code copied from GenRegisterInfo.inc.Andrew Trick2013-02-222-57/+0
| | | | | | | | There's no apparent reason this code was copied from generated source into a .cpp. It sets a bad example for those working on other targets and trying to understand the register info API. llvm-svn: 175849
* Move the eliminateCallFramePseudoInstr method from TargetRegisterInfoEli Bendersky2013-02-2153-569/+541
| | | | | | | | | | | | | | | to TargetFrameLowering, where it belongs. Incidentally, this allows us to delete some duplicated (and slightly different!) code in TRI. There are potentially other layering problems that can be cleaned up as a result, or in a similar manner. The refactoring was OK'd by Anton Korobeynikov on llvmdev. Note: this touches the target interfaces, so out-of-tree targets may be affected. llvm-svn: 175788
* Hexagon: Expand cttz, ctlz, and ctpop for now.Anshuman Dasgupta2013-02-211-0/+5
| | | | llvm-svn: 175783
* Radar numbers don't belong in source code.Evan Cheng2013-02-213-4/+1
| | | | llvm-svn: 175775
* Trivial cleanupBill Schmidt2013-02-211-2/+2
| | | | llvm-svn: 175771
* Large code model support for PowerPC.Bill Schmidt2013-02-215-15/+20
| | | | | | | | | | | Large code model is identical to medium code model except that the addis/addi sequence for "local" accesses is never used. All accesses use the addis/ld sequence. The coding changes are straightforward; most of the patch is taken up with creating variants of the medium model tests for large model. llvm-svn: 175767
* getX86SubSuperRegister has a special mode with High=true for i64 whichEli Bendersky2013-02-211-17/+9
| | | | | | | | | | exists solely to enable it to call itself for i8 with some registers. The proposed patch simplifies the function somewhat to make the High bit only meaningful for the i8 mode, which makes sense. No functional difference (getX86SubSuperRegister is not getting called from anywhere outside with i64 and High=true). llvm-svn: 175762
* R600/SI: inline V_ADD|SUB_F32 patternsChristian Konig2013-02-211-9/+5
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175758
* R600/SI: replace IMPLICIT_DEF with SIOperand.ZEROChristian Konig2013-02-211-1/+1
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175757
* R600/SI: replace SI_V_CNDLT with a patternChristian Konig2013-02-213-31/+5
| | | | | | | | | | | It actually fixes quite a bunch of piglit tests. This is a candidate for the mesa-stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175756
* R600/SI: use patterns for clamp, fabs, fnegChristian Konig2013-02-212-40/+22
| | | | | | | | | | Instead of using custom inserters, it's simpler and should make DAG folding easier. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175755
* R600/SI: add all the other missing asm operands v2Christian Konig2013-02-212-22/+29
| | | | | | | | | v2: put implicit parameters in [] Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175754
* R600/SI: add the missing M*BUF|IMG asm operandsChristian Konig2013-02-211-4/+8
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175753
* R600/SI: add the missing S_* asm operandsChristian Konig2013-02-211-18/+34
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175752
* R600/SI: rework VOP3 classesChristian Konig2013-02-211-14/+14
| | | | | | | | | Order the classes and add asm operands. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175751
* R600/SI: simplify VOPC_* pattern v2Christian Konig2013-02-213-255/+217
| | | | | | | | | | | Fixing asm operation names. v2: fix name of the e64 encoding, also add asm operands Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175750
* R600/SI: rework VOP2_* pattern v2Christian Konig2013-02-212-21/+19
| | | | | | | | | | | Fixing asm operation names. v2: use ZERO constant, also add asm operands Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175749
* R600/SI: rework VOP1_* patterns v2Christian Konig2013-02-211-17/+21
| | | | | | | | | | | Fixing asm operation names. v2: use ZERO constant, also add asm operands Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175748
* R600/SI: add constant for inline zero operandChristian Konig2013-02-211-4/+3
| | | | | | | Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175747
* R600/SI: cleanup SIInstrInfo.td and SIInstrFormat.tdChristian Konig2013-02-212-488/+527
| | | | | | | | | Those two files got mixed up. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Reviewed-by: Michel Dänzer <michel.daenzer@amd.com> llvm-svn: 175746
* R600: Fix for Unigine when MachineSched is enabledTom Stellard2013-02-211-0/+1
| | | | | | | | | | | Fixes for-loop.cl piglit test Patch By: Vincent Lejeune Reviewed-by: Tom Stellard <thomas.stellard@amd.com> NOTE: This is a candidate for the Mesa stable branch. llvm-svn: 175742
* Code review cleanup for r175697Bill Schmidt2013-02-211-11/+7
| | | | llvm-svn: 175739
* R600/SI: Make sure M0 is loaded for V_INTERP_MOV_F32Michel Danzer2013-02-211-1/+2
| | | | | | | NOTE: This is a candidate for the Mesa stable branch. Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175733
* Expand the sel pseudo/macro. This generates basic blocks where previouslyReed Kotler2013-02-213-1/+97
| | | | | | | there were inline br .+4 instructions. Soon everything can enjoy the full instruction scheduling experience. llvm-svn: 175718
* Mips specific standalone assembler addressing mode %hi and %lo.Jack Carter2013-02-211-0/+5
| | | | | | | | | | | | The constructs %hi() and %lo() represent the high and low 16 bits of the address. Because the 16 bit offset field of an LW instruction is interpreted as signed, if bit 15 of the low part is 1 then the low part will act as a negative and 1 needs to be added to the high part. Contributer: Vladimir Medic llvm-svn: 175707
* PPCDAGToDAGISel::PostprocessISelDAG()Bill Schmidt2013-02-211-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the PPCDAGToDAGISel::PostprocessISelDAG virtual method to perform post-selection peephole optimizations on the DAG representation. One optimization is implemented here: folds to clean up complex addressing expressions for thread-local storage and medium code model. It will also be useful for large code model sequences when those are added later. I originally thought about doing this on the MI representation prior to register assignment, but it's difficult to do effective global dead code elimination at that point. DCE is trivial on the DAG representation. A typical example of a candidate code sequence in assembly: addis 3, 2, globalvar@toc@ha addi 3, 3, globalvar@toc@l lwz 5, 0(3) When the final instruction is a load or store with an immediate offset of zero, the offset from the add-immediate can replace the zero, provided the relocation information is carried along: addis 3, 2, globalvar@toc@ha lwz 5, globalvar@toc@l(3) Since the addi can in general have multiple uses, we need to only delete the instruction when the last use is removed. llvm-svn: 175697
* Relocation enablement for PPC DAG postprocessing passBill Schmidt2013-02-214-11/+37
| | | | llvm-svn: 175693
* ELF symbol table field st_other support, Jack Carter2013-02-201-85/+84
| | | | | | | | | | | | | | | | | | | | excluding visibility bits. Mips specific standalone assembler directive "set at". This directive changes the general purpose register that the assembler will use when given the symbolic register name $at. This does not include negative testing. That will come in a future patch. A side affect of this patch recognizes the different GPR register names for temporaries between old abi and new abi so a test case for that is included. Contributer: Vladimir Medic llvm-svn: 175686
* MCParser: Update method names per coding guidelines.Jim Grosbach2013-02-205-74/+74
| | | | | | | | | | | | | | | | | | | s/AddDirectiveHandler/addDirectiveHandler/ s/ParseMSInlineAsm/parseMSInlineAsm/ s/ParseIdentifier/parseIdentifier/ s/ParseStringToEndOfStatement/parseStringToEndOfStatement/ s/ParseEscapedString/parseEscapedString/ s/EatToEndOfStatement/eatToEndOfStatement/ s/ParseExpression/parseExpression/ s/ParseParenExpression/parseParenExpression/ s/ParseAbsoluteExpression/parseAbsoluteExpression/ s/CheckForValidSection/checkForValidSection/ http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly No functional change intended. llvm-svn: 175675
* R600: Update for name changes from r175667.Jim Grosbach2013-02-201-3/+3
| | | | llvm-svn: 175668
* Update TargetLowering ivars for name policy.Jim Grosbach2013-02-207-32/+32
| | | | | | | | | | | http://llvm.org/docs/CodingStandards.html#name-types-functions-variables-and-enumerators-properly ivars should be camel-case and start with an upper-case letter. A few in TargetLowering were starting with a lower-case letter. No functional change intended. llvm-svn: 175667
* Additional fixes for bug 15155.Bill Schmidt2013-02-203-35/+64
| | | | | | | | This handles the cases where the 6-bit splat element is odd, converting to a three-instruction sequence to add or subtract two splats. With this fix, the XFAIL in test/CodeGen/PowerPC/vec_constants.ll is removed. llvm-svn: 175663
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