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* [XCore] Add missing u6 / lu6 instructions.Richard Osborne2013-02-171-2/+18
| | | | | | | These instructions are not targeted by the compiler but they are needed for the MC layer. llvm-svn: 175403
* Return false instead of 0.Jakub Staszak2013-02-171-1/+1
| | | | llvm-svn: 175402
* AArch64: Avoid shifts by 64, that's undefined behavior.Benjamin Kramer2013-02-171-3/+3
| | | | | | No functionality change. llvm-svn: 175400
* Make the visibility of LLVMPPCCompilationCallback work with GCC.Benjamin Kramer2013-02-171-1/+1
| | | | | | | | | | | | GCC warns about the attribute being ignored if it occurs after void*. There seems to be some kind of incompatibility between clang and gcc here, but I can't fathom who's right. void* LLVM_LIBRARY_VISIBILITY foo(); // clang: hidden, gcc: default LLVM_LIBRARY_VISIBILITY void *bar(); // clang: hidden, gcc: hidden void LLVM_LIBRARY_VISIBILITY qux(); // clang: hidden, gcc: hidden llvm-svn: 175394
* Clean up mips16 td file in preparation for massive pseudo lowering work.Reed Kotler2013-02-161-71/+68
| | | | llvm-svn: 175379
* TypoRenato Golin2013-02-161-1/+1
| | | | llvm-svn: 175371
* One more try to make this look nice. I have lots of pseudo lowering Reed Kotler2013-02-162-4/+12
| | | | | | | | as well as 16/32 bit variants to do and so I want this to look nice when I do it. I've been experimenting with this. No new test cases are needed. llvm-svn: 175369
* [msvc x64] Update X86CompilationCallback_Win64.asm corresponding to r175267.NAKAMURA Takumi2013-02-161-2/+2
| | | | llvm-svn: 175363
* Target/R600/CMakeLists.txt: Prune SILowerLiteralConstants.cpp corresponding ↵NAKAMURA Takumi2013-02-161-1/+0
| | | | | | to r175354. llvm-svn: 175361
* Minor cleanups. No functionality change.Jakub Staszak2013-02-161-9/+8
| | | | llvm-svn: 175359
* R600/SI: Add pattern to simplify i64 loadingChristian Konig2013-02-162-0/+9
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175356
* R600/SI: nuke SReg_1 v3Christian Konig2013-02-167-118/+23
| | | | | | | | | | | | | | | | | It's completely unnecessary and can be replace with proper SReg_64 handling instead. This actually fixes a piglit test on SI. v2: use correct register class in addRegisterClass, set special classes as not allocatable v3: revert setting special classes as not allocateable This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175355
* R600/SI: cleanup literal handling v3Christian Konig2013-02-1610-195/+176
| | | | | | | | | | | | | | | | Seems to be allot simpler, and also paves the way for further improvements. v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW, use VGPR0 in dummy EXP, avoid compiler warning, break after encoding the first literal. v3: correctly use V_ADD_F32_e64 This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175354
* R600/SI: replace AllReg_* with [SV]Src_* v2Christian Konig2013-02-163-85/+89
| | | | | | | | | | | | Mark all the operands that can also have an immediate. v2: SOFFSET is also an SSrc_32 operand This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175353
* R600/SI: fix VOPC encoding v2Christian Konig2013-02-161-37/+16
| | | | | | | | | | | | | Previously it only worked because of coincident. v2: fix 64bit versions, use 0x80 (inline 0) instead of SGPR0 for the unused SRC2 This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175352
* R600/SI: move *_Helper definitions to SIInstrFormat.tdChristian Konig2013-02-162-66/+66
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175351
* R600/SI: remove some more unused codeChristian Konig2013-02-162-52/+0
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175350
* R600/structurizer: improve inverting conditionsChristian Konig2013-02-161-1/+39
| | | | | | | | | | Stop adding more instructions than necessary. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175349
* R600/structurizer: improve loop handlingChristian Konig2013-02-161-196/+148
| | | | | | | | | | Generate more than one loop if it seems to make sense. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175348
* R600/structurizer: improve finding condition valuesChristian Konig2013-02-161-9/+22
| | | | | | | | | | Using the new NearestCommonDominator class. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175347
* R600/structurizer: improve PHI value findingChristian Konig2013-02-161-0/+6
| | | | | | | | | | Using the new NearestCommonDominator class. This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175346
* R600/structurizer: add class to find the Nearest Common DominatorChristian Konig2013-02-161-0/+66
| | | | | | | | This is a candidate for the stable branch. Signed-off-by: Christian König <christian.koenig@amd.com> Reviewed-by: Tom Stellard <thomas.stellard@amd.com> llvm-svn: 175345
* Use a different scheme to chose 16/32 variants. This scheme is moreReed Kotler2013-02-162-11/+7
| | | | | | | consistent with how BuildMI works. No new tests needed. All should work the same as before. llvm-svn: 175342
* Reinitialize the ivars in the subtarget so that they can be reset with the ↵Bill Wendling2013-02-164-73/+89
| | | | | | new features. llvm-svn: 175336
* [ms-inline asm] Do not omit the frame pointer if we have ms-inline assembly.Chad Rosier2013-02-161-1/+1
| | | | | | | | | | | If the frame pointer is omitted, and any stack changes occur in the inline assembly, e.g.: "pusha", then any C local variable or C argument references will be incorrect. I pass no judgement on anyone who would do such a thing. ;) rdar://13218191 llvm-svn: 175334
* [mips] Remove SDNPWantParent from the list of SDNodeProperties.Akira Hatanaka2013-02-162-17/+14
| | | | | | No functionality change intended. llvm-svn: 175325
* Temporary revert of 175320.Bill Wendling2013-02-154-90/+74
| | | | llvm-svn: 175322
* Reinitialize the ivars in the subtarget.Bill Wendling2013-02-154-74/+90
| | | | | | | When we're recalculating the feature set of the subtarget, we need to have the ivars in their initial state. llvm-svn: 175320
* Support changing the subtarget features in ARM.Bill Wendling2013-02-152-4/+29
| | | | llvm-svn: 175315
* Use the 'target-features' and 'target-cpu' attributes to reset the subtarget ↵Bill Wendling2013-02-152-41/+67
| | | | | | | | | | features. If two functions require different features (e.g., `-mno-sse' vs. `-msse') then we want to honor that, especially during LTO. We can do that by resetting the subtarget's features depending upon the 'target-feature' attribute. llvm-svn: 175314
* [ms-inline asm] Adjust the EndLoc to account for the ']'.Chad Rosier2013-02-151-1/+2
| | | | llvm-svn: 175312
* [mips] Clean up class MipsCCInfo.Akira Hatanaka2013-02-152-58/+74
| | | | | | No functionality change intended. llvm-svn: 175310
* [mips] Split SelectAddr, which was used to match address patterns, into twoAkira Hatanaka2013-02-153-18/+71
| | | | | | | | | | | functions. Set AddedComplexity to determine the order in which patterns are matched. This simplifies selection of floating point loads/stores. No functionality change intended. llvm-svn: 175300
* Remove a final dependency on the form field in tablegen; which is a remnantReed Kotler2013-02-152-6/+10
| | | | | | | of the old jit and which we don't intend to support in mips16 or micromips. This dependency is for the testing of whether an instruction is a pseudo. llvm-svn: 175297
* Hexagon: Set appropriate TSFlags to the loads/stores with global address toJyotsna Verma2013-02-151-33/+25
| | | | | | | | support constant extension. This patch doesn't introduce any functionality changes. llvm-svn: 175280
* AArch64: add branch fixup pass.Tim Northover2013-02-156-0/+652
| | | | | | | | | | | | | This is essentially a stripped-down version of the ConstandIslands pass (which always had these two functions), providing just the features necessary for correctness. In particular there needs to be a way to resolve the situation where a conditional branch's destination block ends up out of range. This issue crops up when self-hosting for AArch64. llvm-svn: 175269
* Give these callbacks hidden visibility. It is better to not export them moreRafael Espindola2013-02-152-4/+6
| | | | | | | than we need to and some ELF linkers complain about directly accessing symbols with default visibility. llvm-svn: 175268
* Don't make assumptions about the mangling of static functions in extern "C"Rafael Espindola2013-02-152-27/+17
| | | | | | | | blocks. We still don't have consensus if we should try to change clang or the standard, but llvm should work with compilers that implement the current standard and mangle those functions. llvm-svn: 175267
* Make helpers static. Add missing include so LLVMInitializeObjCARCOpts gets C ↵Benjamin Kramer2013-02-151-1/+1
| | | | | | linkage. llvm-svn: 175264
* AArch64: remove ConstantIsland pass & put literals in separate section.Tim Northover2013-02-1512-1610/+83
| | | | | | | | This implements the review suggestion to simplify the AArch64 backend. If we later discover that we *really* need the extra complexity of the ConstantIslands pass for performance reasons it can be resurrected. llvm-svn: 175258
* AArch64: refactor frame handling to use movz/movk for overlarge offsets.Tim Northover2013-02-151-12/+29
| | | | | | | | In the near future litpools will be in a different section, which means that any access to them is at least two instructions. This makes the case for a movz/movk pair (if total offset <= 32-bits) even more compelling. llvm-svn: 175257
* Fix minor mips16 issues in directives for function prologue. Probably this doesReed Kotler2013-02-151-7/+10
| | | | | | | not matter but makes it more gcc compatible which avoids possible subtle problems. Also, turned back on a disabled check in helloworld.ll. llvm-svn: 175237
* [mips] Disallow moving load/store instructions past volatile instructions.Akira Hatanaka2013-02-141-1/+1
| | | | | | | Unfortunately, I wasn't able to create a test case that demonstrates the problem I was trying to fix with this patch. llvm-svn: 175226
* [mips] Replace usage of SmallSet with BitVector, which is used to keep track ofAkira Hatanaka2013-02-141-86/+83
| | | | | | | defined and used registers. Also add a few helper functions to simplify the code. llvm-svn: 175224
* [mips] Fix comments and coding style violations. Declare functions to be const.Akira Hatanaka2013-02-141-64/+47
| | | | llvm-svn: 175222
* The ARM NEON vector compare instructions take three arguments. However, the Joel Jones2013-02-141-0/+5
| | | | | | | | | | | | | | assembler should also accept a two arg form, as the docuemntation specifies that the first (destination) register is optional. This patch uses TwoOperandAliasConstraint to add the two argument form. It also fixes an 80-column formatting problem in: test/MC/ARM/neon-bitwise-encoding <rdar://problem/12909419> Clang rejects ARM NEON assembly instructions llvm-svn: 175221
* The operand listing is very much outdated.Eli Bendersky2013-02-141-5/+2
| | | | llvm-svn: 175220
* [mips] Simplify code in function Filler::findDelayInstr.Akira Hatanaka2013-02-141-38/+29
| | | | | | | | 1. Define and use function terminateSearch. 2. Use MachineBasicBlock::iterator instead of MachineBasicBlock::instr_iterator. 3. Delete the line which checks whether an instruction is a pseudo. llvm-svn: 175219
* Simplify code. Remove "else after return".Jakub Staszak2013-02-141-5/+4
| | | | llvm-svn: 175212
* Hexagon: Change insn class to support instruction encoding.Jyotsna Verma2013-02-145-259/+252
| | | | | | | | This patch doesn't introduce any functionality changes. It adds some new fields to the Hexagon instruction classes and changes their layout to support instruction encoding. llvm-svn: 175205
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