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* Fix PIC16 comments referencing copyRegToReg.Jakob Stoklund Olesen2010-07-111-3/+3
| | | | llvm-svn: 108082
* Replace copyRegToReg with copyPhysReg for PIC16.Jakob Stoklund Olesen2010-07-112-24/+17
| | | | llvm-svn: 108081
* Replace copyRegToReg with copyPhysReg for MSP430.Jakob Stoklund Olesen2010-07-112-25/+17
| | | | llvm-svn: 108080
* Replace copyRegToReg with copyPhysReg for MBlaze.Jakob Stoklund Olesen2010-07-112-14/+10
| | | | llvm-svn: 108079
* Replace copyRegToReg with copyPhysReg for ARM.Jakob Stoklund Olesen2010-07-116-146/+84
| | | | llvm-svn: 108078
* Replace copyRegToReg with copyPhysReg for Blackfin.Jakob Stoklund Olesen2010-07-112-55/+57
| | | | llvm-svn: 108077
* X86InstrInfo::copyRegToReg is dead. Long live copyPhysReg!Jakob Stoklund Olesen2010-07-112-171/+0
| | | | llvm-svn: 108076
* Use COPY in X86FastISel::X86SelectRet.Jakob Stoklund Olesen2010-07-111-6/+4
| | | | | | | Don't try a cross-class copy. That is very unlikely anywy since return value registers are usually register class friendly. (%EAX, %XMM0, etc). llvm-svn: 108074
* Fix va_arg for doubles. With this patch VAARG nodes always contain theRafael Espindola2010-07-111-0/+4
| | | | | | | | | | | | | | | correct alignment information, which simplifies ExpandRes_VAARG a bit. The patch introduces a new alignment information to TargetLoweringInfo. This is needed since the two natural candidates cannot be used: * The 's' in target data: If this is set to the minimal alignment of any argument, getCallFrameTypeAlignment would return 4 for doubles on ARM for example. * The getTransientStackAlignment method. It is possible for an architecture to have argument less aligned than what we maintain the stack pointer. llvm-svn: 108072
* Use COPY in FastISel everywhere it is safe and trivial.Jakob Stoklund Olesen2010-07-111-18/+8
| | | | | | | The remaining copyRegToReg calls actually check the return value (shock!), so we cannot trivially replace them with COPY instructions. llvm-svn: 108069
* Replace copyRegToReg with copyPhysReg for Mips.Jakob Stoklund Olesen2010-07-112-56/+68
| | | | llvm-svn: 108066
* Replace copyRegToReg with copyPhysReg for Alpha.Jakob Stoklund Olesen2010-07-112-28/+15
| | | | llvm-svn: 108065
* Use COPY in targetsJakob Stoklund Olesen2010-07-103-22/+8
| | | | llvm-svn: 108063
* Don't emit st(0)/st(1) copies as FpMOV instructions. Use FpSET_ST? instead.Jakob Stoklund Olesen2010-07-102-83/+65
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on a patch by Rafael Espíndola. Attempt to make the FpSET_ST1 hack more robust, but we are still relying on FpSET_ST0 preceeding it. This is only for supporting really weird x87 inline asm. We support: FpSET_ST0 INLINEASM FpSET_ST0 FpSET_ST1 INLINEASM with and without kills on the arguments. We don't support: FpSET_ST1 FpSET_ST0 INLINEASM nor FpSET_ST1 INLINEASM Just Don't Do It! llvm-svn: 108047
* Add parentheses yet again to satisfy GCC's warnings.Chandler Carruth2010-07-101-3/+3
| | | | llvm-svn: 108043
* Reapply bottom-up fast-isel, with several fixes for x86-32:Dan Gohman2010-07-108-94/+301
| | | | | | | | | - Check getBytesToPopOnReturn(). - Eschew ST0 and ST1 for return values. - Fix the PIC base register initialization so that it doesn't ever fail to end up the top of the entry block. llvm-svn: 108039
* An x86 function returns a floating point value in st(0), and we must make sureJakob Stoklund Olesen2010-07-101-18/+26
| | | | | | | | | it is popped, even if it is ununsed. A CopyFromReg node is too weak to represent the required sideeffect, so insert an FpGET_ST0 instruction directly instead. This will matter when CopyFromReg gets lowered to a generic COPY instruction. llvm-svn: 108037
* Declare YMM subregisters in the right way! Thanks JakobBruno Cardoso Lopes2010-07-091-2/+1
| | | | llvm-svn: 108022
* Add AVX 256-bit packed MOVNT variantsBruno Cardoso Lopes2010-07-091-0/+22
| | | | llvm-svn: 108021
* Remember the *_TC opcodes for load/storeJakob Stoklund Olesen2010-07-091-0/+4
| | | | llvm-svn: 108020
* Add AVX 256-bit unpack and interleaveBruno Cardoso Lopes2010-07-091-0/+17
| | | | llvm-svn: 108017
* Automatically fold COPY instructions into stack load/store.Jakob Stoklund Olesen2010-07-092-2/+2
| | | | llvm-svn: 108012
* Fix a few testsJakob Stoklund Olesen2010-07-091-1/+1
| | | | llvm-svn: 108011
* In the presence of variable sized objects, allocate an emergency spill slot.Jim Grosbach2010-07-091-3/+10
| | | | | | rdar://8131327 llvm-svn: 108008
* Start the support for AVX instructions with 256-bit %ymm registers. A couple ofBruno Cardoso Lopes2010-07-098-18/+99
| | | | | | | | | | | | | | | notes: - The instructions are being added with dummy placeholder patterns using some 256 specifiers, this is not meant to work now, but since there are some multiclasses generic enough to accept them, when we go for codegen, the stuff will be already there. - Add VEX encoding bits to support YMM - Add MOVUPS and MOVAPS in the first round - Use "Y" as suffix for those Instructions: MOVUPSYrr, ... - All AVX instructions in X86InstrSSE.td will move soon to a new X86InstrAVX file. llvm-svn: 107996
* --- Reverse-merging r107947 into '.':Bob Wilson2010-07-095-205/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | U utils/TableGen/FastISelEmitter.cpp --- Reverse-merging r107943 into '.': U test/CodeGen/X86/fast-isel.ll U test/CodeGen/X86/fast-isel-loads.ll U include/llvm/Target/TargetLowering.h U include/llvm/Support/PassNameParser.h U include/llvm/CodeGen/FunctionLoweringInfo.h U include/llvm/CodeGen/CallingConvLower.h U include/llvm/CodeGen/FastISel.h U include/llvm/CodeGen/SelectionDAGISel.h U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/CallingConvLower.cpp U lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp U lib/CodeGen/SelectionDAG/FunctionLoweringInfo.cpp U lib/CodeGen/SelectionDAG/FastISel.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp U lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp U lib/CodeGen/SelectionDAG/InstrEmitter.cpp U lib/CodeGen/SelectionDAG/TargetLowering.cpp U lib/Target/XCore/XCoreISelLowering.cpp U lib/Target/XCore/XCoreISelLowering.h U lib/Target/X86/X86ISelLowering.cpp U lib/Target/X86/X86FastISel.cpp U lib/Target/X86/X86ISelLowering.h llvm-svn: 107987
* Merge VEX enums with other x86 enum forms. Also fix all checks of which VEXBruno Cardoso Lopes2010-07-092-22/+17
| | | | | | fields to use. llvm-svn: 107952
* Fix the memoperand offsets in code generated for va_start.Dan Gohman2010-07-091-3/+3
| | | | llvm-svn: 107948
* have the mc lowering process handle a few tail call forms, lowering them toChris Lattner2010-07-093-13/+19
| | | | | | | | | | | | | jumps where possible and turning the TAILCALL marker in the instruction asm string into a proper comment. This eliminates a FIXME and is on the path to finishing: rdar://7639610 - eliminate encoding and asm info for TAILJMPd TAILJMPr TAILJMPn, etc. However, I can't eliminate the encodings for these instructions because the JIT still exists and has its own copy of the encoder, sigh. llvm-svn: 107946
* Print "dregpair" NEON operands with a space between them, for readability andBob Wilson2010-07-091-1/+1
| | | | | | consistency with other instructions that have lists of register operands. llvm-svn: 107944
* Re-apply bottom-up fast-isel, with fixes. Be very careful to avoid emittingDan Gohman2010-07-095-70/+205
| | | | | | a DBG_VALUE after a terminator, or emitting any instructions before an EH_LABEL. llvm-svn: 107943
* Factor out x86 segment override prefix encoding, and also use it for VEXBruno Cardoso Lopes2010-07-091-18/+33
| | | | llvm-svn: 107942
* reject pseudo instructions early in the encoder.Chris Lattner2010-07-092-11/+5
| | | | llvm-svn: 107939
* Remove trailing whitespaces from fileBruno Cardoso Lopes2010-07-091-66/+66
| | | | llvm-svn: 107937
* Change LEA to have 5 operands for its memory operand, justChris Lattner2010-07-0815-160/+98
| | | | | | | | | | | like all other instructions, even though a segment is not allowed. This resolves a bunch of gross hacks in the encoder and makes LEA more consistent with the rest of the instruction set. No functionality change. llvm-svn: 107934
* add some long-overdue enums to refer to the parts of the 5-operandChris Lattner2010-07-086-44/+56
| | | | | | X86 memory operand. llvm-svn: 107925
* Remember the VR64 register classJakob Stoklund Olesen2010-07-081-0/+2
| | | | llvm-svn: 107920
* Rework segment prefix emission code to handle segmentsChris Lattner2010-07-081-47/+41
| | | | | | | | | | | | in memory operands at the same type as hard coded segments. This fixes problems where we'd emit the segment override after the REX prefix on instructions like: mov %gs:(%rdi), %rax This fixes rdar://8127102. I have several cleanup patches coming next. llvm-svn: 107917
* introduce a new X86II::getMemoryOperandNo method, whichChris Lattner2010-07-081-12/+71
| | | | | | | | | returns the start of the memory operand for an instruction. Introduce a new "X86AddrSegment" enum to reduce # magic numbers referring to X86 memory operand layout. llvm-svn: 107916
* Switch SPU calling convention (function arguments) Kalle Raiskila2010-07-084-118/+52
| | | | | | to a Tablegen implementation. llvm-svn: 107913
* Check for FiniteOnlyFPMath as well.Evan Cheng2010-07-081-1/+1
| | | | llvm-svn: 107904
* Teach the x86 floating point stackifier to handle COPY instructions.Jakob Stoklund Olesen2010-07-081-1/+36
| | | | | | | | | | | This pass runs before COPY instructions are passed to copyPhysReg, so we simply translate COPY to the proper pseudo instruction. Note that copyPhysReg does not handle floating point stack copies. Once COPY is used everywhere, this can be cleaned up a bit, and most of the pseudo instructions can be removed. llvm-svn: 107899
* Implement X86InstrInfo::copyPhysRegJakob Stoklund Olesen2010-07-082-0/+64
| | | | llvm-svn: 107898
* The NEONPreAllocPass should never have to assign fixed registers anymore.Bob Wilson2010-07-081-34/+1
| | | | | | This pass can go away entirely soon. llvm-svn: 107892
* For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap theBob Wilson2010-07-081-2/+2
| | | | | | | words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements instead. llvm-svn: 107890
* Clean up a comment.Bob Wilson2010-07-081-5/+5
| | | | llvm-svn: 107882
* Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen2010-07-083-10/+8
| | | | | | | | | EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. llvm-svn: 107879
* Remove references to INSERT_SUBREG after de-SSA.Jakob Stoklund Olesen2010-07-081-8/+6
| | | | | | | Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of INSERT_SUBREG. llvm-svn: 107878
* Teach instcombine to transformBenjamin Kramer2010-07-081-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | (X >s -1) ? C1 : C2 and (X <s 0) ? C2 : C1 into ((X >>s 31) & (C2 - C1)) + C1, avoiding the conditional. This optimization could be extended to take non-const C1 and C2 but we better stay conservative to avoid code size bloat for now. for int sel(int n) { return n >= 0 ? 60 : 100; } we now generate sarl $31, %edi andl $40, %edi leal 60(%rdi), %eax instead of testl %edi, %edi movl $60, %ecx movl $100, %eax cmovnsl %ecx, %eax llvm-svn: 107866
* A slight reworking of the custom patterns for x86-64 tpoff codegen andEric Christopher2010-07-081-9/+11
| | | | | | | | correct the testcase for valid assembly. Needs more tests. llvm-svn: 107860
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