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* Implement a MachineFunctionPass to fix the mul instructionRafael Espindola2006-09-194-1/+74
| | | | llvm-svn: 30485
* item doneChris Lattner2006-09-191-11/+0
| | | | llvm-svn: 30483
* Fold the PPCISD shifts when presented with 0 inputs. This occurs for codeChris Lattner2006-09-191-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | like: long long test(long long X, int Y) { return 1ULL << Y; } long long test2(long long X, int Y) { return -1LL << Y; } which we used to compile to: _test: li r2, 1 subfic r3, r5, 32 li r4, 0 addi r6, r5, -32 srw r3, r2, r3 slw r4, r4, r5 slw r6, r2, r6 or r3, r4, r3 slw r4, r2, r5 or r3, r3, r6 blr _test2: li r2, -1 subfic r3, r5, 32 addi r6, r5, -32 srw r3, r2, r3 slw r4, r2, r5 slw r2, r2, r6 or r3, r4, r3 or r3, r3, r2 blr Now we produce: _test: li r2, 1 addi r3, r5, -32 subfic r4, r5, 32 slw r3, r2, r3 srw r4, r2, r4 or r3, r4, r3 slw r4, r2, r5 blr _test2: li r2, -1 subfic r3, r5, 32 addi r6, r5, -32 srw r3, r2, r3 slw r4, r2, r5 slw r2, r2, r6 or r3, r4, r3 or r3, r3, r2 blr llvm-svn: 30479
* A pass to remove the worst of the replay trap offenders, and as a bonus, ↵Andrew Lenharth2006-09-183-0/+146
| | | | | | align basic blocks when it is free to do so llvm-svn: 30467
* Jump tables on AlphaAndrew Lenharth2006-09-183-2/+38
| | | | llvm-svn: 30463
* add a note. Our 64-bit shifts are ~30% slower than gcc'sChris Lattner2006-09-181-1/+2
| | | | llvm-svn: 30457
* This is closer to what we really want.Chris Lattner2006-09-181-2/+3
| | | | llvm-svn: 30451
* Added some eye-candy for Subtarget type checkingAnton Korobeynikov2006-09-177-8/+42
| | | | | | Added X86 StdCall & FastCall calling conventions. Codegen will follow. llvm-svn: 30446
* Small fixes for supporting dll* linkage typesAnton Korobeynikov2006-09-171-2/+2
| | | | llvm-svn: 30441
* add a note noticed through source inspectionChris Lattner2006-09-161-3/+30
| | | | llvm-svn: 30418
* add a noteChris Lattner2006-09-161-0/+3
| | | | llvm-svn: 30406
* add a nate noteChris Lattner2006-09-151-0/+6
| | | | llvm-svn: 30399
* Remove a unnecessary check.Evan Cheng2006-09-141-1/+0
| | | | llvm-svn: 30382
* add a noteChris Lattner2006-09-141-0/+25
| | | | llvm-svn: 30377
* Adding dllimport, dllexport and external weak linkage types.Anton Korobeynikov2006-09-1410-10/+159
| | | | | | | | | DLL* linkages got full (I hope) codegeneration support in C & both x86 assembler backends. External weak linkage added for future use, we don't provide any codegeneration, etc. support for it. llvm-svn: 30374
* add note about switch loweringChris Lattner2006-09-131-0/+29
| | | | llvm-svn: 30308
* Skip over first operand when determining REX prefix for two-address code.Evan Cheng2006-09-131-7/+14
| | | | llvm-svn: 30300
* Turn X < 0 -> TEST X,X jsChris Lattner2006-09-131-8/+11
| | | | llvm-svn: 30294
* The sense of this branch was inverted :(Chris Lattner2006-09-131-1/+1
| | | | llvm-svn: 30293
* add shifts to addressing mode 1Rafael Espindola2006-09-136-32/+81
| | | | llvm-svn: 30291
* Fix a regression in the 32-bit port from the 64-bit port landing.Chris Lattner2006-09-131-2/+2
| | | | | | | | | | | | | | | | | | | | | We now compile CodeGen/X86/lea-2.ll into: _test: movl 4(%esp), %eax movl 8(%esp), %ecx leal -5(%ecx,%eax,4), %eax ret instead of: _test: movl 4(%esp), %eax leal (,%eax,4), %eax addl 8(%esp), %eax addl $4294967291, %eax ret llvm-svn: 30288
* new noteChris Lattner2006-09-131-0/+32
| | | | llvm-svn: 30286
* new noteChris Lattner2006-09-131-0/+13
| | | | llvm-svn: 30285
* Compile X > -1 -> text X,X; js destChris Lattner2006-09-132-28/+23
| | | | | | This implements CodeGen/X86/jump_sign.ll. llvm-svn: 30283
* Reflects MachineConstantPoolEntry changes.Evan Cheng2006-09-128-11/+12
| | | | llvm-svn: 30279
* add a noteChris Lattner2006-09-121-0/+14
| | | | llvm-svn: 30271
* Testcase noticed from PR906Chris Lattner2006-09-111-0/+34
| | | | llvm-svn: 30269
* add compilable testcaseChris Lattner2006-09-111-1/+6
| | | | llvm-svn: 30268
* implement SRL and MULRafael Espindola2006-09-111-0/+9
| | | | llvm-svn: 30262
* add the correct fallback for ARMDAGToDAGISel::SelectAddrMode1Rafael Espindola2006-09-111-6/+3
| | | | llvm-svn: 30261
* partial implementation of the ARM Addressing Mode 1Rafael Espindola2006-09-115-37/+74
| | | | llvm-svn: 30252
* call AsmPrinter::doInitialization in ARMAsmPrinter::doInitializationRafael Espindola2006-09-111-0/+1
| | | | llvm-svn: 30246
* Updates.Evan Cheng2006-09-112-154/+0
| | | | llvm-svn: 30245
* Update README file.Evan Cheng2006-09-111-98/+3
| | | | llvm-svn: 30244
* X86ISD::CMP now produces a chain as well as a flag. Make that the chainEvan Cheng2006-09-115-157/+131
| | | | | | | operand of a conditional branch to allow load folding into CMP / TEST instructions. llvm-svn: 30241
* Behold, more work on relocations. Things are looking pretty good now.Nate Begeman2006-09-102-40/+70
| | | | llvm-svn: 30240
* Removed unnecessary Mangler creation.Anton Korobeynikov2006-09-101-1/+0
| | | | llvm-svn: 30239
* Add cbe support for powiChris Lattner2006-09-091-0/+10
| | | | llvm-svn: 30226
* First pass at supporting relocations. Relocations are written correctly toNate Begeman2006-09-083-21/+88
| | | | | | | the file now, however the relocated address is currently wrong. Fixing that will require some deep pondering. llvm-svn: 30207
* Fixed a FuseTwoAddrInst() bug: consider GlobalAddress and JumpTableIndexEvan Cheng2006-09-081-6/+11
| | | | | | in addition to immediate operands. llvm-svn: 30205
* implement shl and sraRafael Espindola2006-09-081-0/+12
| | | | llvm-svn: 30191
* Use __USER_LABEL_PREFIX__ to get the prefix added by the current host.Chris Lattner2006-09-081-15/+14
| | | | llvm-svn: 30190
* add the eor (xor) instructionRafael Espindola2006-09-081-0/+5
| | | | llvm-svn: 30189
* Missing tabJim Laskey2006-09-081-1/+1
| | | | llvm-svn: 30188
* implement unconditional branchesRafael Espindola2006-09-081-0/+4
| | | | | | fix select.ll llvm-svn: 30186
* Remove TEST64mr. It's same as TEST64rm since and is commutative.Evan Cheng2006-09-081-3/+0
| | | | llvm-svn: 30178
* Committing X86-64 support.Evan Cheng2006-09-0825-462/+3603
| | | | llvm-svn: 30177
* We actually do support object file writing, so don't return true (error)Nate Begeman2006-09-081-3/+1
| | | | llvm-svn: 30173
* - Identify a vector_shuffle that can be turned into an undef, e.g.Evan Cheng2006-09-081-15/+41
| | | | | | | | | shuffle V1, <undef>, <undef, undef, 4, 5> - Fix some suspicious logic into LowerVectorShuffle that cause less than optimal code by failing to identify MOVL (move to lowest element of a vector). llvm-svn: 30171
* 1. Remove condition on delete.Jim Laskey2006-09-0713-37/+57
| | | | | | | | 2. Protect and outline createTargetAsmInfo. 3. Misc. kruft. llvm-svn: 30169
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