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* Simplify the datalayout string of ARM and AArch64.Rafael Espindola2013-12-122-4/+4
| | | | | | | | No functionality change. Reviewed by Tim Northover. llvm-svn: 197172
* Simplify the SystemZ datalayout string.Rafael Espindola2013-12-121-2/+1
| | | | | | Reviewed by Richard Sandiford. llvm-svn: 197170
* Use "a" instead of "a0" in DataLayout.Rafael Espindola2013-12-123-3/+3
| | | | | | It means exactly the same and is just a bit shorter. llvm-svn: 197169
* Switch to the new MingW ABI.Rafael Espindola2013-12-122-5/+5
| | | | | | | GCC 4.7 changed the MingW ABI. On the LLVM side it means that sret functions don't pop the stack. llvm-svn: 197163
* [AArch64] Removed unnecessary copy patterns with v1fx types.Chad Rosier2013-12-124-27/+3
| | | | | | | | | | | | | | - Copy patterns with float/double types are enough. - Fix typos in test case names that were using v1fx. - There is no ACLE intrinsic that uses v1f32 type. And there is no conflict of neon and non-neon ovelapped operations with this type, so there is no need to support operations with this type. - Remove v1f32 from FPR32 register and disallow v1f32 as a legal type for operations. Patch by Ana Pazos! llvm-svn: 197159
* Added new X86 patterns to select SSE scalar fp arithmetic instructions fromAndrea Di Biagio2013-12-121-0/+83
| | | | | | | | | | | | | | | | | | | | | | a vector packed single/double fp operation followed by a vector insert. The effect is that the backend coverts the packed fp instruction followed by a vectro insert into a SSE or AVX scalar fp instruction. For example, given the following code: __m128 foo(__m128 A, __m128 B) { __m128 C = A + B; return (__m128) {c[0], a[1], a[2], a[3]}; } previously we generated: addps %xmm0, %xmm1 movss %xmm1, %xmm0 we now generate: addss %xmm1, %xmm0 llvm-svn: 197145
* typo in commentGabor Greif2013-12-121-2/+2
| | | | llvm-svn: 197136
* [AArch64]Fix the problem that AArch64 backend fails to select ↵Hao Liu2013-12-121-3/+37
| | | | | | scalar_to_vector of vector types having more than one element. llvm-svn: 197135
* Check for null pointer before dereferencing. A careless typo on my part.Reed Kotler2013-12-121-2/+2
| | | | | | | I don't know why this did not show up earlier. This code has been around for ages. llvm-svn: 197119
* Resubmit r196544: Apply transformation on OS X 10.9+ and iOS 7.0+: pow(10, ↵Yi Jiang2013-12-121-0/+25
| | | | | | x) ―> __exp10(x) llvm-svn: 197109
* Remove unused multiclass from PPCInstrInfo.tdHal Finkel2013-12-121-14/+0
| | | | llvm-svn: 197100
* Improve instruction scheduling for the PPC POWER7Hal Finkel2013-12-127-3/+337
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Aside from a few minor latency corrections, the major change here is a new hazard recognizer which focuses on better dispatch-group formation on the POWER7. As with the PPC970's hazard recognizer, the most important thing it does is avoid load-after-store hazards within the same dispatch group. It uses the POWER7's special dispatch-group-terminating nop instruction (instead of inserting multiple regular nop instructions). This new hazard recognizer makes use of the scheduling dependency graph itself, built using AA information, to robustly detect the possibility of load-after-store hazards. significant test-suite performance changes (the error bars are 99.5% confidence intervals based on 5 test-suite runs both with and without the change -- speedups are negative): speedups: MultiSource/Benchmarks/FreeBench/pcompress2/pcompress2 -0.55171% +/- 0.333168% MultiSource/Benchmarks/TSVC/CrossingThresholds-dbl/CrossingThresholds-dbl -17.5576% +/- 14.598% MultiSource/Benchmarks/TSVC/Reductions-dbl/Reductions-dbl -29.5708% +/- 7.09058% MultiSource/Benchmarks/TSVC/Reductions-flt/Reductions-flt -34.9471% +/- 11.4391% SingleSource/Benchmarks/BenchmarkGame/puzzle -25.1347% +/- 11.0104% SingleSource/Benchmarks/Misc/flops-8 -17.7297% +/- 9.79061% SingleSource/Benchmarks/Shootout-C++/ary3 -35.5018% +/- 23.9458% SingleSource/Regression/C/uint64_to_float -56.3165% +/- 25.4234% SingleSource/UnitTests/Vectorizer/gcc-loops -18.5309% +/- 6.8496% regressions: MultiSource/Benchmarks/ASCI_Purple/SMG2000/smg2000 18.351% +/- 12.156% SingleSource/Benchmarks/Shootout-C++/methcall 27.3086% +/- 14.4733% llvm-svn: 197099
* [AArch64] Refactor NEON floating-point Max/Min/Maxnm/Minnm across vector AArch64Chad Rosier2013-12-111-2/+2
| | | | | | intrinsics to use f32 types, rather than their vector equivalents. llvm-svn: 197090
* Fix the PPC subsumes-predicate checkHal Finkel2013-12-111-0/+4
| | | | | | | | | For one predicate to subsume another, they must both check the same condition register. Failure to check this prerequisite was causing miscompiles. Fixes PR18003. llvm-svn: 197089
* [AArch64] Add NEON scalar floating-point compare LLVM AArch64 intrinsics thatChad Rosier2013-12-111-16/+18
| | | | | | use f32/f64 types, rather than their vector equivalents. llvm-svn: 197068
* [AArch64] Refactor the NEON scalar floating-point reciprocal step andChad Rosier2013-12-111-11/+11
| | | | | | | floating-point reciprocal square root step LLVM AArch64 intrinsics to use f32/f64 types, rather than their vector equivalents. llvm-svn: 197067
* [AArch64] Refactor the NEON scalar floating-point reciprocal estimate, floating-Chad Rosier2013-12-111-10/+19
| | | | | | | | point reciprocal exponent, and floating-point reciprocal square root estimate LLVM AArch64 intrinsics to use f32/f64 types, rather than their vector equivalents. llvm-svn: 197066
* Don't set unused variable.Rafael Espindola2013-12-111-1/+0
| | | | llvm-svn: 197064
* R600: Re-format Processors.tdTom Stellard2013-12-111-0/+48
| | | | | | | This makes it a little easier to read. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197058
* R600: Register AMDGPUCFGStructurizer passTom Stellard2013-12-113-10/+23
| | | | | | | This enables -print-before-all to dump MachineInstrs after it is run. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197057
* R600: Register R600EmitClauseMarkers passTom Stellard2013-12-113-9/+19
| | | | | | | This enables -print-before-all to dump MachineInstrs after it is run. Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 197056
* [arm] Implement ARM .arch directive.Logan Chien2013-12-114-2/+223
| | | | llvm-svn: 197052
* ARM: constrain register-class in fast-iselTim Northover2013-12-111-1/+3
| | | | | | | | The tests were no longer using fast-isel at all (MachO needs an "ios" rather than "darwin" triple at the moment and Linux needs ARM mode). Once that was corrected, the verifier complained about a t2ADDri created for the alloca. llvm-svn: 197046
* AVX-512: Removed "z" suffix from AVX-512 instructions, since it is ↵Elena Demikhovsky2013-12-112-99/+102
| | | | | | | | | incompatible with GCC. I moved a test from avx512-vbroadcast-crash.ll to avx512-vbroadcast.ll I defined HasAVX512 predicate as AssemblerPredicate. It means that you should invoke llvm-mc with "-mcpu=knl" to get encoding for AVX-512 instructions. I need this to let AsmMatcher to set different encoding for AVX and AVX-512 instructions that have the same mnemonic and operands (all scalar instructions). llvm-svn: 197041
* [SystemZ] Optimize fcmp X, 0 in cases where X is also negatedRichard Sandiford2013-12-111-4/+30
| | | | | | | In such cases it's often better to test the result of the negation instead, since the negation also sets CC. llvm-svn: 197032
* Distinguish and choose 16 or 32 bit forms of save/restore for Mips16.Reed Kotler2013-12-112-4/+16
| | | | llvm-svn: 196999
* [AArch64 NEON] Get instruction BSL matched to VSELECT.Kevin Qin2013-12-113-24/+17
| | | | llvm-svn: 196998
* Move mips' datalayout computation out of line and add comments.Rafael Espindola2013-12-111-11/+31
| | | | llvm-svn: 196996
* Move Sparc's getDataLayout out of line and add comments.Rafael Espindola2013-12-112-10/+24
| | | | llvm-svn: 196990
* Prune redundant dependencies in LLVMBuild.txt.NAKAMURA Takumi2013-12-1119-19/+19
| | | | llvm-svn: 196988
* Move PPC's getDataLayoutString out of line and document it better.Rafael Espindola2013-12-112-17/+39
| | | | llvm-svn: 196987
* Revert the backend fatal error from r196939Reid Kleckner2013-12-101-6/+0
| | | | | | | | | | | | | | The combination of inline asm, stack realignment, and dynamic allocas turns out to be too common to reject out of hand. ASan inserts empy inline asm fragments and uses aligned allocas. Compiling any trivial function containing a dynamic alloca with ASan is enough to trigger the check. XFAIL the test cases that would be miscompiled and add one that uses the relevant functionality. llvm-svn: 196986
* Refactor the computation of the x86 datalayout.Rafael Espindola2013-12-101-14/+47
| | | | llvm-svn: 196976
* Use llvm_unreachable instead of assert(0)Matt Arsenault2013-12-109-20/+18
| | | | llvm-svn: 196971
* on darwin<10, fallback to .weak_definition (PPC,X86)David Fang2013-12-104-3/+18
| | | | | | .weak_def_can_be_hidden was not yet supported by the system assembler llvm-svn: 196970
* [AArch64] Refactor the NEON floating-point absolute difference LLVM AArch64Chad Rosier2013-12-101-2/+11
| | | | | | intrinsic to use f32/f64 types, rather than their vector equivalents. llvm-svn: 196965
* [AArch64] Refactor the NEON signed/unsigned floating-point convert to ↵Chad Rosier2013-12-101-2/+2
| | | | | | | | fixed-point LLVM AArch64 intrinsics to use f32/f64, rather than their vector equivalents. llvm-svn: 196964
* [AArch64] Overload NEON signed/unsigned floating-point convert to fixed-pointChad Rosier2013-12-101-16/+10
| | | | | | and fixed-point convert to floating-point LLVM AArch64 intrinsics. llvm-svn: 196963
* [AArch64] Overload NEON signed/unsigned integer convert to floating-pointChad Rosier2013-12-101-8/+5
| | | | | | LLVM AArch64 intrinsics. llvm-svn: 196962
* Reland "Fix miscompile of MS inline assembly with stack realignment"Reid Kleckner2013-12-102-13/+16
| | | | | | | | | | | This re-lands commit r196876, which was reverted in r196879. The tests have been fixed to pass on platforms with a stack alignment larger than 4. Update to clang side tests will land shortly. llvm-svn: 196939
* Make Triple's isOSBinFormatXXX functions partition triple-space.Tim Northover2013-12-107-22/+18
| | | | | | | | | | | Most users would be surprised if "isCOFF" and "isMachO" were simultaneously true, unless they'd put the compiler in a box with a gun attached to a photon detector. This makes sure precisely one of the three formats is true for any triple and simplifies some target logic based on that. llvm-svn: 196934
* [AArch64] Refactor the Neon vector/scalar floating-point convert intrinsics soChad Rosier2013-12-101-13/+30
| | | | | | that they use float/double rather than the vector equivalents when appropriate. llvm-svn: 196930
* [AArch64] Refactor the Neon vector/scalar floating-point convert implementation.Chad Rosier2013-12-101-16/+16
| | | | | | Specifically, reuse the ARM intrinsics when possible. llvm-svn: 196926
* Ensure that the backend no longer emits unnecessary vector insert instructionsAndrea Di Biagio2013-12-101-0/+125
| | | | | | | | | | | | | | | | | | | | | | immediately after SSE scalar fp instructions like addss or mulss. Added patterns to select SSE scalar fp arithmetic instructions from a scalar fp operation followed by a blend. For example, given the following code: __m128 foo(__m128 A, __m128 B) { A[0] += B[0]; return A; } previously we generated: addss %xmm0, %xmm1 movss %xmm1, %xmm0 now we generate: addss %xmm1, %xmm0 llvm-svn: 196925
* R600: Fix an infinite loop when trying to reorganize export/tex vector inputVincent Lejeune2013-12-101-5/+8
| | | | llvm-svn: 196923
* R600: Fix input modifiers lost for CaymanVincent Lejeune2013-12-101-0/+18
| | | | llvm-svn: 196922
* Next step in Mips16 prologue/epilogue cleanup.Reed Kotler2013-12-104-18/+56
| | | | | | | | Save S2(reg 18) only when we are calling floating point stubs that have a return value of float or complex. Some more work to make this better but this is the first step. llvm-svn: 196921
* AVX-512: changed intrinsics for mask operationsElena Demikhovsky2013-12-102-16/+28
| | | | llvm-svn: 196918
* AVX-512: Changed intrinsics of VPCONFLICT to match GCC builtin formElena Demikhovsky2013-12-102-19/+39
| | | | llvm-svn: 196914
* [mips][msa] Correct sld and sldi builtins.Daniel Sanders2013-12-101-13/+21
| | | | | | | | | | | | | Summary: The result register of these instructions is also the first operand. Reviewers: jacksprat, dsanders Reviewed By: dsanders Differential Revision: http://llvm-reviews.chandlerc.com/D2362 Differential Revision: http://llvm-reviews.chandlerc.com/D2363 llvm-svn: 196910
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