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* ARM: Correctly align arguments after a byval struct is passed on the stackOliver Stannard2014-03-054-62/+121
| | | | llvm-svn: 202985
* Enable integrated assembler on OpenBSD/PPC32 by default, too.Joerg Sonnenberger2014-03-051-1/+2
| | | | | | From Brad Smith. llvm-svn: 202967
* This patch implements .set dsp directive and sets appropriate feature ↵Vladimir Medic2014-03-053-0/+17
| | | | | | bits.This directive is a counterpart of -mattr=dsp command line option with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202966
* Remove a special character in comment that accidentially got committed.Evan Cheng2014-03-041-1/+1
| | | | llvm-svn: 202905
* MS asm: Attempt to parse variables followed by a bracketed displacementReid Kleckner2014-03-041-2/+34
| | | | | | | | | | This is required to include MSVC's <atomic> header, which we do now in LLVM. Tests forthcoming in Clang, since that's where we test semantic inline asm changes. llvm-svn: 202865
* X86: 80-columnSaleem Abdulrasool2014-03-041-1/+2
| | | | llvm-svn: 202863
* [PowerPC] support powerpc64le as syntax-checking target (pass2)Will Schmidt2014-03-041-0/+1
| | | | | | | | Register the Asm Printer for the ppc64le target. This fills in a spot that was missed in an earlier change (r187179). llvm-svn: 202861
* [XCore] Fix call of absolute address.Richard Osborne2014-03-041-3/+2
| | | | | | | | | | | | | | | Previously for: tail call void inttoptr (i64 65536 to void ()*)() nounwind We would emit: bl 65536 The immediate operand of the bl instruction is a relative offset so it is wrong to use the absolute address here. llvm-svn: 202860
* [mips][msa] Correct the behaviour of the COPY_FW pseudo on lanes 2 and 3.Daniel Sanders2014-03-041-1/+1
| | | | | | | | | | Summary: Previously, attempting to extract lanes 2 and 3 would actually extract lane 1. The MSA CodeGen tests only covered lanes 0 and 1. Differential Revision: http://llvm-reviews.chandlerc.com/D2935 llvm-svn: 202848
* [Modules] Move the NoFolder into the IR library as it createsChandler Carruth2014-03-041-1/+1
| | | | | | instructions. llvm-svn: 202834
* [Modules] Move CFG.h to the IR library as it defines graph traits overChandler Carruth2014-03-043-3/+3
| | | | | | IR types. llvm-svn: 202827
* [Modules] Move ValueMap to the IR library. While this class does notChandler Carruth2014-03-043-3/+3
| | | | | | | | | | | | directly care about the Value class (it is templated so that the key can be any arbitrary Value subclass), it is in fact concretely tied to the Value class through the ValueHandle's CallbackVH interface which relies on the key type being some Value subclass to establish the value handle chain. Ironically, the unittest is already in the right library. llvm-svn: 202824
* [Modules] Move ValueHandle into the IR library where Value itself lives.Chandler Carruth2014-03-042-2/+2
| | | | | | | | | | | Move the test for this class into the IR unittests as well. This uncovers that ValueMap too is in the IR library. Ironically, the unittest for ValueMap is useless in the Support library (honestly, so was the ValueHandle test) and so it already lives in the IR unittests. Mmmm, tasty layering. llvm-svn: 202821
* [Modules] Move CallSite into the IR library where it belogs. It isChandler Carruth2014-03-044-4/+4
| | | | | | | abstracting between a CallInst and an InvokeInst, both of which are IR concepts. llvm-svn: 202816
* [Modules] Move GetElementPtrTypeIterator into the IR library. As itsChandler Carruth2014-03-043-3/+3
| | | | | | | | | name might indicate, it is an iterator over the types in an instruction in the IR.... You see where this is going. Another step of modularizing the support library. llvm-svn: 202815
* [Modules] Move InstIterator out of the Support library, where it had noChandler Carruth2014-03-044-4/+4
| | | | | | | | | | | | | business. This header includes Function and BasicBlock and directly uses the interfaces of both classes. It has to do with the IR, it even has that in the name. =] Put it in the library it belongs to. This is one step toward making LLVM's Support library survive a C++ modules bootstrap. llvm-svn: 202814
* [cleanup] Re-sort all the includes with utils/sort_includes.py.Chandler Carruth2014-03-0410-12/+11
| | | | llvm-svn: 202811
* This patch implements .set mips32r2 directive and sets appropriate feature ↵Vladimir Medic2014-03-043-0/+35
| | | | | | bits. It also introduces helper functions that are used to set and clear feature bits as necessary. This directive is a counterpart of -mips32r2 command line options with the exception that it does not influence elf header flags. The usage example is gives in test file. llvm-svn: 202807
* Cleaning up a bunch of pre-Visual C++ 2012 build hacks.Yaron Keren2014-03-043-23/+0
| | | | llvm-svn: 202806
* [AArch64]Fix improper diagnostics about offset range of load/store instructions.Kevin Qin2014-03-041-2/+2
| | | | llvm-svn: 202775
* MC: Fix Intel assembly parser for [global + offset]Reid Kleckner2014-03-041-15/+27
| | | | | | | | | We were dropping the displacement on the floor if we also had some immediate offset. Should fix PR19033. llvm-svn: 202774
* Revert "[AArch64] This is a work in progress to provide a machine description"Chad Rosier2014-03-045-546/+185
| | | | | | This reverts commit ff717c8fc786a0cfa1602982b91895fa09e514fc. llvm-svn: 202773
* [AArch64] This is a work in progress to provide a machine descriptionChad Rosier2014-03-035-185/+546
| | | | | | | | | | | | | | | | | | | for the Cortex-A53 subtarget in the AArch64 backend. This patch lays the ground work to annotate each AArch64 instruction (no NEON yet) with a list of SchedReadWrite types. The patch also provides the Cortex-A53 processor resources, maps those the the default SchedReadWrites, and provides basic latency. NEON support will be added in a subsequent patch with proper forwarding logic. Verification was done by setting the pre-RA scheduler to linearize to better gauge the effect of the MIScheduler. Even without modeling the forward logic, the results show a modest improvement for Cortex-A53. Reviewers: apazos, mcrosier, atrick Patch by Dave Estes <cestes@codeaurora.org>! llvm-svn: 202767
* [mips] Prevent %lo relocation being used on MSA loads and stores.Daniel Sanders2014-03-036-75/+102
| | | | | | | | | | | | | | | | | Summary: Parts of the compiler still believed MSA load/stores have a 16-bit offset when it is actually 10-bit. Corrected this, and fixed a closely related issue this uncovered where load/stores with 10-bit and 12-bit offsets (MSA and microMIPS respectively) could not load/store using offsets from the stack/frame pointer. They accepted frameindex+offset, but not frameindex by itself. Reviewers: jacksprat, matheusalmeida Reviewed By: jacksprat Differential Revision: http://llvm-reviews.chandlerc.com/D2888 llvm-svn: 202717
* [mips] support FK_Data_2 and FK_Data_8 to fix big-endian debug dataEd Maste2014-03-031-0/+4
| | | | | | | | | This fixes invalid lengths in .debug_aranges on big-endian mips64 (lengths appear to be left-shifted by 32 bits) and in .debug_loc. Differential Revision: http://llvm-reviews.chandlerc.com/D2517 llvm-svn: 202716
* Fixing a build failure reported by certain buildbots. This will disable ↵Vladimir Medic2014-03-031-1/+1
| | | | | | jalx instruction for micromips target. llvm-svn: 202715
* This patch implements jalx instruction for Mips architecture.This ↵Vladimir Medic2014-03-031-0/+1
| | | | | | instruction executes a procedure call within the current 256 MB-aligned region and change the ISA Mode from MIPS32 to microMIPS32 or MIPS16e. Usage samples for assembler and dissasembler are provided as well. llvm-svn: 202706
* [Sparc] Add trap on integer condition codes (Ticc) instructions to Sparc ↵Venkatraman Govindaraju2014-03-024-1/+101
| | | | | | backend. llvm-svn: 202670
* [Sparc] Add return/rett instruction to Sparc backend.Venkatraman Govindaraju2014-03-024-0/+46
| | | | llvm-svn: 202666
* [Sparc] Add support for decoding jmpl/retl/ret instruction.Venkatraman Govindaraju2014-03-023-2/+47
| | | | llvm-svn: 202663
* [Sparc] Add fcmpe* instructions to Sparc backend.Venkatraman Govindaraju2014-03-023-6/+28
| | | | llvm-svn: 202661
* [Sparc] Add VIS instructions to sparc backend.Venkatraman Govindaraju2014-03-024-8/+290
| | | | llvm-svn: 202660
* Add a PPC inline asm constraint type for single CR bitsHal Finkel2014-03-021-0/+8
| | | | | | | | | | | | | | | | | Now that the PowerPC backend can track individual CR bits as first-class registers, we should also have a way of allocating them for inline asm statements. Because these registers are only one bit, if an output variable is implicitly cast to a larger integer size, we'll get an any_extend to that larger type (this is part of the existing target-independent logic). As a result, regardless of the size of the output type, only the first bit is meaningful. The constraint identifier "wc" has been chosen for this purpose. Although gcc does not currently support allocating individual CR bits, this identifier choice has been coordinated with the gcc PowerPC team, and will be marked as reserved for this purpose in the gcc constraints.md file. llvm-svn: 202657
* [C++11] Replace llvm::tie with std::tie.Benjamin Kramer2014-03-021-1/+2
| | | | | | The old implementation is no longer needed in C++11. llvm-svn: 202644
* [C++11] Replace llvm::next and llvm::prior with std::next and std::prev.Benjamin Kramer2014-03-0250-205/+176
| | | | | | Remove the old functions. llvm-svn: 202636
* [SparcV9] Adds support for branch on integer register instructions (BPr) and ↵Venkatraman Govindaraju2014-03-028-1/+165
| | | | | | conditional moves on integer register (MOVr/FMOVr). llvm-svn: 202628
* AVX-512: Fixed extract_vector_elt for v8i1 vectorElena Demikhovsky2014-03-024-6/+14
| | | | llvm-svn: 202624
* Switch all uses of LLVM_OVERRIDE to just use 'override' directly.Craig Topper2014-03-0247-312/+282
| | | | llvm-svn: 202621
* Switch all uses of LLVM_FINAL to just use 'final', and remove the macro.Craig Topper2014-03-026-6/+6
| | | | llvm-svn: 202618
* [Sparc] Add support for parsing branches and conditional move instructions ↵Venkatraman Govindaraju2014-03-024-44/+89
| | | | | | with %fcc1-%fcc3 conditional registers. llvm-svn: 202616
* [Sparc] Make floating point branch instruction formats to accept %fcc0-%fcc1 ↵Venkatraman Govindaraju2014-03-024-34/+40
| | | | | | | | conditional registers as input. No functionality change. llvm-svn: 202614
* [Sparc] Add support for parsing fcmp with %fcc registers.Venkatraman Govindaraju2014-03-028-12/+78
| | | | llvm-svn: 202610
* [Sparc] Add register class for floating point conditional flags (%fcc0 - %fcc3).Venkatraman Govindaraju2014-03-023-11/+16
| | | | llvm-svn: 202604
* [SparcV9] Add support for parsing branch instructions with prediction.Venkatraman Govindaraju2014-03-017-44/+156
| | | | llvm-svn: 202602
* Remove extra truncs/exts around i32 bit operations on PPC64Hal Finkel2014-03-011-12/+82
| | | | | | | | | | | | | | | | | | | | | | | | | This generalizes the code to eliminate extra truncs/exts around i1 bit operations to also do the same on PPC64 for i32 bit operations. This eliminates a fairly prevalent code wart: int foo(int a) { return a == 5 ? 7 : 8; } On PPC64, because of the extension implied by the ABI, this would generate: cmplwi 0, 3, 5 li 12, 8 li 4, 7 isel 3, 4, 12, 2 rldicl 3, 3, 0, 32 blr where the 'rldicl 3, 3, 0, 32', the extension, is completely unnecessary. At least for the single-BB case (which is all that the DAG combine mechanism can handle), this unnecessary extension is no longer generated. llvm-svn: 202600
* [Sparc] Add support for parsing annulled branch instructions.Venkatraman Govindaraju2014-03-017-13/+80
| | | | llvm-svn: 202599
* [Sparc] Add support for parsing sparcv9 instructions addc/subc/addccc/subccc.Venkatraman Govindaraju2014-03-014-7/+13
| | | | llvm-svn: 202598
* [Sparc] Add missing ALU instruction patterns.Venkatraman Govindaraju2014-03-011-0/+35
| | | | llvm-svn: 202597
* Now that we have C++11, turn simple functors into lambdas and remove a ton ↵Benjamin Kramer2014-03-012-28/+13
| | | | | | | | of boilerplate. No intended functionality change. llvm-svn: 202588
* [Sparc] Add support to decode unimp instruction.Venkatraman Govindaraju2014-03-011-2/+2
| | | | llvm-svn: 202581
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