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* X86: @llvm.frameaddress should defer to SelectionDAG for Win CFIDavid Majnemer2015-02-101-2/+7
| | | | llvm-svn: 228754
* X86: Make @llvm.frameaddress work correctly with Windows unwind codesDavid Majnemer2015-02-103-5/+34
| | | | | | | | | Simply loading or storing the frame pointer is not sufficient for Windows targets. Instead, create a synthetic frame object that we will lower later. References to this synthetic object will be replaced with the correct reference to the frame address. llvm-svn: 228748
* Fix up r228725, missed change in PPCSubtarget definitionBill Schmidt2015-02-101-6/+6
| | | | llvm-svn: 228728
* [PowerPC] Fix reverted patch r227976 to avoid register assignment issuesBill Schmidt2015-02-1011-114/+379
| | | | | | | | | | | | | | | | | | | See full discussion in http://reviews.llvm.org/D7491. We now hide the add-immediate and call instructions together in a separate pseudo-op, which is tagged to define GPR3 and clobber the call-killed registers. The PPCTLSDynamicCall pass prior to RA now expands this op into the two separate addi and call ops, with explicit definitions of GPR3 on both instructions, and explicit clobbers on the call instruction. The pass is now marked as requiring and preserving the LiveIntervals and SlotIndexes analyses, and fixes these up after the replacement sequences are introduced. Self-hosting has been verified on LE P8 and BE P7 with various optimization levels, etc. It has also been verified with the --no-tls-optimize flag workaround removed. llvm-svn: 228725
* X86: Emit Win64 SaveXMM opcodes at the right offset in the right orderDavid Majnemer2015-02-101-19/+18
| | | | | | | | | | | Walk the instructions marked FrameSetup and consider any stores of XMM registers to the stack as needing a SaveXMM opcode. This fixes PR22521. Differential Revision: http://reviews.llvm.org/D7527 llvm-svn: 228724
* [PowerPC] Support the (old) cntlz instruction aliasHal Finkel2015-02-101-0/+3
| | | | | | | Some old assembly code uses the cntlz alias for cntlzw, binutils supports this, and we should too. Fixes PR22519. llvm-svn: 228719
* [Hexagon] Adding vector load with post-increment instructions. Adding ↵Colin LeMahieu2015-02-104-4/+319
| | | | | | decoder function for 64bit control register class. llvm-svn: 228708
* [mips][microMIPS] Implement movep instructionZoran Jovanovic2015-02-107-0/+237
| | | | | | Differential Revision: http://reviews.llvm.org/D7465 llvm-svn: 228703
* [X86][AVX2] Missing AVX2 memory folding instructionsSimon Pilgrim2015-02-101-3/+35
| | | | | | | | Added most of the missing vector folding patterns for AVX2 (as well as fixing the vpermpd and verpmq patterns) Differential Revision: http://reviews.llvm.org/D7492 llvm-svn: 228688
* [X86][XOP] Added XOP memory folding patterns + testsSimon Pilgrim2015-02-101-5/+100
| | | | | | | | | | This patch adds the complete AMD Bulldozer XOP instruction set to the memory folding pattern tables for stack folding, etc. Note: Many of the XOP instructions have multiple table entries as it can fold loads from different sources. Differential Revision: http://reviews.llvm.org/D7484 llvm-svn: 228685
* [mips][microMIPS] Fix disassembling of 16-bit microMIPS instructions LWM16 ↵Jozef Kolek2015-02-102-7/+25
| | | | | | | | and SWM16 Differential Revision: http://reviews.llvm.org/D7436 llvm-svn: 228683
* [X86][FastIsel] Avoid introducing legacy SSE instructions if the target has AVX.Andrea Di Biagio2015-02-101-28/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch teaches X86FastISel how to select AVX instructions for scalar float/double convert operations. Before this patch, X86FastISel always selected legacy SSE instructions for FPExt (from float to double) and FPTrunc (from double to float). For example: \code define double @foo(float %f) { %conv = fpext float %f to double ret double %conv } \end code Before (with -mattr=+avx -fast-isel) X86FastIsel selected a CVTSS2SDrr which is legacy SSE: cvtss2sd %xmm0, %xmm0 With this patch, X86FastIsel selects a VCVTSS2SDrr instead: vcvtss2sd %xmm0, %xmm0, %xmm0 Added test fast-isel-fptrunc-fpext.ll to check both the register-register and the register-memory float/double conversion variants. Differential Revision: http://reviews.llvm.org/D7438 llvm-svn: 228682
* [X86] Preserve mem refs on newly created 'Store' node instead of 'Load' node ↵Craig Topper2015-02-101-1/+1
| | | | | | | | | | when handling store unfolding. Bug spotted by Steve King. I have no idea how to test this. llvm-svn: 228672
* [X86] Remove unnecessary alignment checks from the load folding tables.Craig Topper2015-02-101-44/+44
| | | | llvm-svn: 228671
* X86: Emit an ABI compliant prologue and epilogue for Win64David Majnemer2015-02-101-79/+132
| | | | | | | | | | | | | | Win64 has specific contraints on what valid prologues and epilogues look like. This constraint is born from the flexibility and descriptiveness of Win64's unwind opcodes. Prologues previously emitted by LLVM could not be represented by the unwind opcodes, preventing operations powered by stack unwinding to successfully work. Differential Revision: http://reviews.llvm.org/D7520 llvm-svn: 228641
* Migrate PPCAsmPrinter's subtarget from reference to pointer inEric Christopher2015-02-101-48/+49
| | | | | | preparation for making it MachineFunction dependent. llvm-svn: 228638
* Fix the clang -Werror build (-Wunused-variable)David Blaikie2015-02-101-3/+0
| | | | llvm-svn: 228635
* [Hexagon] Adding missing load instructions and removing an unused multiclass ↵Colin LeMahieu2015-02-091-38/+169
| | | | | | parameter. llvm-svn: 228630
* [Hexagon] Factoring classes out of some load patterns and deleting some ↵Colin LeMahieu2015-02-091-40/+87
| | | | | | unused ones. llvm-svn: 228627
* [Hexagon] Removing more V4 predicates since V4 is the required minimum.Colin LeMahieu2015-02-0912-470/+226
| | | | llvm-svn: 228614
* [Hexagon] Removing v2-4 flags. V4 is the minimum supported version.Colin LeMahieu2015-02-094-93/+64
| | | | llvm-svn: 228605
* [Hexagon] Factoring classes out of store patterns.Colin LeMahieu2015-02-091-34/+47
| | | | llvm-svn: 228602
* [Hexagon] Formatting v5 TD file. Removing commented defs.Colin LeMahieu2015-02-091-38/+28
| | | | llvm-svn: 228598
* [Hexagon] Cleaning up definition formatting.Colin LeMahieu2015-02-091-85/+85
| | | | llvm-svn: 228593
* This change implements the following three logical vector operations:Kit Barton2015-02-091-0/+25
| | | | | | | | | | | | veqv (vector equivalence) vnand vorc I increased the AddedComplexity for these instructions to 500 to ensure they are generated instead of issuing other VSX instructions. Phabricator review: http://reviews.llvm.org/D7469 llvm-svn: 228580
* rename variable to give it some meaning; remove obvious comments; NFCSanjay Patel2015-02-091-12/+12
| | | | llvm-svn: 228579
* fix comment that didn't match the code; remove unnecessary braces; NFCSanjay Patel2015-02-091-4/+3
| | | | llvm-svn: 228578
* [X86] Remove 256-bit and 512-bit memop pattern fragments. They are no longer ↵Craig Topper2015-02-092-14/+2
| | | | | | used. llvm-svn: 228563
* [X86] Remove 'memop' uses from AVX512. Use 'load' instead.Craig Topper2015-02-091-81/+71
| | | | llvm-svn: 228562
* [X86] Remove the remaining uses of memop from AVX and AVX2 instruction ↵Craig Topper2015-02-082-237/+211
| | | | | | patterns. AVX and AVX2 can handle unaligned loads being folded so we can just use 'load' llvm-svn: 228551
* fix typos; NFCSanjay Patel2015-02-081-3/+3
| | | | llvm-svn: 228529
* Moved AVX2 vbroadcast (reg) instruction foldings under the correct grouping. ↵Simon Pilgrim2015-02-081-3/+3
| | | | | | NFC. llvm-svn: 228526
* ARM & AArch64: teach LowerVSETCC that output type size may differ from input.Tim Northover2015-02-082-18/+27
| | | | | | | | | | | | | | | | | | While various DAG combines try to guarantee that a vector SETCC operation will have the same output size as input, there's nothing intrinsic to either creation or LegalizeTypes that actually guarantees it, so the function needs to be ready to handle a mismatch. Fortunately this is easy enough, just extend or truncate the naturally compared result. I couldn't reproduce the failure in other backends that I know have SIMD, so it's probably only an issue for these two due to shared heritage. Should fix PR21645. llvm-svn: 228518
* [X86] Add register use/def for wrmsr and rdmsr.Craig Topper2015-02-071-0/+2
| | | | llvm-svn: 228515
* [X86] Add GETSEC instruction.Craig Topper2015-02-071-0/+6
| | | | llvm-svn: 228514
* [X86][AVX] Added missing stack folding support + test for vptest ymm instructionSimon Pilgrim2015-02-071-0/+1
| | | | llvm-svn: 228509
* Fix typos; NFC.Andrea Di Biagio2015-02-071-4/+4
| | | | llvm-svn: 228493
* [PowerPC] Handle loop predecessor invokesHal Finkel2015-02-071-4/+12
| | | | | | | | | | If a loop predecessor has an invoke as its terminator, and the return value from that invoke is used to determine the loop iteration space, then we can't insert a computation based on that value in the loop predecessor prior to the terminator (oops). If there's such an invoke, or just no predecessor for that matter, insert a new loop preheader. llvm-svn: 228488
* [AArch64] Use the source location of the IR branch when creating BccAhmed Bougacha2015-02-061-2/+2
| | | | | | | | | | | | | | | | | | from a conditional branch fed by an add/sub/mul-with-overflow node. We previously used the SDLoc of the overflow node, for no good reason. In some cases, this led to the Bcc and B terminators having different source orders, and DBG_VALUEs being inserted between them. The real issue is with the code that can't handle DBG_VALUEs between terminators: the few places affected by this will be fixed soon. In the meantime, fixing the SDLoc is a positive change no matter what. No tests, as I have no idea how to get .loc emitted for branches? rdar://19347133 llvm-svn: 228463
* Revert "r227976 - [PowerPC] Yet another approach to __tls_get_addr" and ↵Hal Finkel2015-02-0611-234/+108
| | | | | | | | | | | | | | related fixups Unfortunately, even with the workaround of disabling the linker TLS optimizations in Clang restored (which has already been done), this still breaks self-hosting on my P7 machine (-O3 -DNDEBUG -mcpu=native). Bill is currently working on an alternate implementation to address the TLS issue in a way that also fully elides the linker bug (which, unfortunately, this approach did not fully), so I'm reverting this now. llvm-svn: 228460
* use local variables; NFCSanjay Patel2015-02-061-3/+2
| | | | llvm-svn: 228452
* Test commit to see if it triggers an email to llvm-commits. No change.Cameron Esfahani2015-02-061-0/+1
| | | | llvm-svn: 228442
* Don't dllexport declarationsReid Kleckner2015-02-061-2/+2
| | | | | | Fixes PR22488 llvm-svn: 228411
* Make helper functions/classes/globals static. NFC.Benjamin Kramer2015-02-065-13/+18
| | | | llvm-svn: 228410
* AArch64PromoteConstant: Modernize and resolve some Use<->User confusion.Benjamin Kramer2015-02-061-87/+63
| | | | | | NFC. llvm-svn: 228399
* R600/SI: Don't enable WQM for V_INTERP_* instructions v2Michel Danzer2015-02-061-6/+0
| | | | | | | | | Doesn't seem necessary anymore. I think this was mostly compensating for not enabling WQM for texture sampling instructions. v2: Add test coverage Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 228373
* R600/SI: Also enable WQM for image opcodes which calculate LOD v3Michel Danzer2015-02-066-56/+79
| | | | | | | | | | | | | If whole quad mode isn't enabled for these, the level of detail is calculated incorrectly for pixels along diagonal triangle edges, causing artifacts. v2: Use a TSFlag instead of lots of switch cases v3: Add test coverage Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=88642 Reviewed-by: Tom Stellard <tom@stellard.net> llvm-svn: 228372
* [Hexagon] Renaming v4 compare-and-jump instructions.Colin LeMahieu2015-02-053-46/+44
| | | | llvm-svn: 228349
* [Hexagon] Deleting unused patterns.Colin LeMahieu2015-02-051-188/+0
| | | | llvm-svn: 228348
* [Hexagon] Simplifying and formatting several patterns. Changing a pattern ↵Colin LeMahieu2015-02-052-154/+88
| | | | | | multiply to be expanded. llvm-svn: 228347
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