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* Changes to ARM tail calls, mostly cosmetic.Dale Johannesen2010-07-083-8/+20
| | | | | | | | | Add explicit testcases for tail calls within the same module. Duplicate some code to humor those who think .w doesn't apply on ARM. Leave this disabled on Thumb1, and add some comments explaining why it's hard and won't gain much. llvm-svn: 107851
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-085-193/+69
| | | | | | Debug info intrinsics win for now. llvm-svn: 107850
* fix copies to/from GR8_ABCD_H even moreJakob Stoklund Olesen2010-07-071-1/+3
| | | | llvm-svn: 107832
* grammarJim Grosbach2010-07-071-1/+1
| | | | llvm-svn: 107831
* Handle cases where the post-RA scheduler may move instructions between theJim Grosbach2010-07-071-6/+21
| | | | | | | | | address calculation instructions leading up to a jump table when we're trying to convert them into a TB[H] instruction in Thumb2. This realistically shouldn't happen much, if at all, for well formed inputs, but it's more correct to handle it. rdar://7387682 llvm-svn: 107830
* finish up support for callw: PR7195Chris Lattner2010-07-071-1/+1
| | | | llvm-svn: 107826
* Implement the major chunk of PR7195: support for 'callw'Chris Lattner2010-07-076-11/+36
| | | | | | | in the integrated assembler. Still some discussion to be done. llvm-svn: 107825
* Add more assembly opcodes for SSE compare instructionsBruno Cardoso Lopes2010-07-071-8/+32
| | | | llvm-svn: 107823
* Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument ↵Evan Cheng2010-07-076-9/+9
| | | | | | for consistency sake. llvm-svn: 107820
* Print undefined/unknown debug value as "undef".Devang Patel2010-07-071-1/+6
| | | | llvm-svn: 107818
* grammar and trailing whitespaceJim Grosbach2010-07-071-6/+6
| | | | llvm-svn: 107811
* Allow copies between GR8_ABCD_L and GR8_ABCD_H.Jakob Stoklund Olesen2010-07-071-0/+3
| | | | | | This fixes PR7540. llvm-svn: 107809
* Implement bottom-up fast-isel. This has the advantage of not requiringDan Gohman2010-07-071-22/+42
| | | | | | a separate DCE pass over MachineInstrs. llvm-svn: 107804
* Add X86FastISel support for return statements. This entails refactoringDan Gohman2010-07-075-12/+78
| | | | | | | a bunch of stuff, to allow the target-independent calling convention logic to be employed. llvm-svn: 107800
* Add AVX AES instructionsBruno Cardoso Lopes2010-07-071-26/+70
| | | | llvm-svn: 107798
* Give FunctionLoweringInfo an MBB member, avoiding the need to pass itDan Gohman2010-07-071-57/+95
| | | | | | | | around everywhere, and also give it an InsertPt member, to enable isel to operate at an arbitrary position within a block, rather than just appending to a block. llvm-svn: 107791
* Simplify FastISel's constructor by giving it a FunctionLoweringInfoDan Gohman2010-07-073-71/+19
| | | | | | | | | instance, rather than pointers to all of FunctionLoweringInfo's members. This eliminates an NDEBUG ABI sensitivity. llvm-svn: 107789
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-0726-53/+125
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Add AVX SSE4.2 instructionsBruno Cardoso Lopes2010-07-071-114/+179
| | | | llvm-svn: 107752
* Use only one multiclass to pinsrq instructionsBruno Cardoso Lopes2010-07-072-38/+20
| | | | llvm-svn: 107750
* Now that almost all SSE4.1 AVX instructions are added, move code around to ↵Bruno Cardoso Lopes2010-07-072-361/+374
| | | | | | more appropriate sections. No functionality changes llvm-svn: 107749
* Add AVX SSE4.1 insertps, ptest and movntdqa instructionsBruno Cardoso Lopes2010-07-071-18/+39
| | | | llvm-svn: 107747
* Add AVX SSE4.1 extractps and pinsr instructionsBruno Cardoso Lopes2010-07-071-35/+67
| | | | llvm-svn: 107746
* Also use REG_SEQUENCE for VTBX instructions.Bob Wilson2010-07-072-24/+30
| | | | llvm-svn: 107743
* Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's whereJim Grosbach2010-07-071-2/+4
| | | | | | they've been tested to work. llvm-svn: 107742
* Add AVX SSE4.1 Extract Integer instructionsBruno Cardoso Lopes2010-07-071-0/+11
| | | | llvm-svn: 107740
* By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing ratherJim Grosbach2010-07-061-0/+2
| | | | | | | than assuming a target will custom lower them. Targets which do so should exlicitly mark them as having custom lowerings. PR7454. llvm-svn: 107734
* Use REG_SEQUENCE nodes to make the table registers for VTBL instructions beBob Wilson2010-07-062-10/+61
| | | | | | allocated to consecutive registers. llvm-svn: 107730
* Accept RIP-relative symbols with 'i' constraint, andDale Johannesen2010-07-062-2/+3
| | | | | | | print the (%rip) only if the 'a' modifier is present. PR 7528. llvm-svn: 107727
* Track defs for all aliases in NEONMoveFix.Jakob Stoklund Olesen2010-07-061-2/+2
| | | | | | | This means that an instruction defining an S register will affect the domain of the parent D register. llvm-svn: 107725
* Add the rest of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-061-0/+17
| | | | llvm-svn: 107723
* Add part of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-061-0/+15
| | | | llvm-svn: 107720
* Fix comment from previous patchBruno Cardoso Lopes2010-07-061-1/+1
| | | | llvm-svn: 107717
* Add AVX vblendvpd, vblendvps and vpblendvb instructionsBruno Cardoso Lopes2010-07-064-10/+61
| | | | | | Update VEX encoding to support those new instructions llvm-svn: 107715
* CanLowerReturn doesn't need a SelectionDAG; it just needs an LLVMContext.Dan Gohman2010-07-064-6/+6
| | | | | | SelectBasicBlock doesn't needs its BasicBlock argument. llvm-svn: 107712
* Propagate debug loc.Devang Patel2010-07-0615-42/+50
| | | | llvm-svn: 107710
* Represent NEON load/store alignments in bytes, not bits.Bob Wilson2010-07-063-7/+13
| | | | llvm-svn: 107701
* Reapply r107655 with fixes; insert the pseudo instruction intoDan Gohman2010-07-0612-205/+245
| | | | | | | the block before calling the expansion hook. And don't put EFLAGS in a mbb's live-in list twice. llvm-svn: 107691
* Fix PR7545 crash.Devang Patel2010-07-061-3/+3
| | | | llvm-svn: 107678
* Don't create neon moves in CopyRegToReg. NEONMoveFixPass will do the conversionRafael Espindola2010-07-061-4/+6
| | | | | | if profitable. llvm-svn: 107673
* Revert r107655.Dan Gohman2010-07-0612-244/+204
| | | | llvm-svn: 107668
* Make getMinimalPhysRegClass' comment mention what makes it differentDan Gohman2010-07-061-1/+2
| | | | | | from getPhysicalRegisterRegClass. llvm-svn: 107660
* Fix a bunch of custom-inserter functions to handle the case whereDan Gohman2010-07-0612-204/+244
| | | | | | the pseudo instruction is not at the end of the block. llvm-svn: 107655
* Fix up -fstack-protector on linux to use the segmentEric Christopher2010-07-062-0/+27
| | | | | | | | | registers. Split out testcases per architecture and os now. Patch from Nelson Elhage. llvm-svn: 107640
* Have the X86 backend use Triple instead of a string and some enums.Eric Christopher2010-07-053-64/+38
| | | | llvm-svn: 107625
* Remove some unused/redundant code.Kalle Raiskila2010-07-052-20/+0
| | | | llvm-svn: 107622
* more tidying.Chris Lattner2010-07-051-2/+1
| | | | llvm-svn: 107615
* some notes about suboptimal insertps'sChris Lattner2010-07-051-0/+31
| | | | llvm-svn: 107613
* rip out even more sporadic v2f32 support.Chris Lattner2010-07-053-19/+1
| | | | llvm-svn: 107610
* rip out the various v2f32 "mmx" handling logic, now that Chris Lattner2010-07-051-6/+6
| | | | | | v2f32 is illegal on x86. llvm-svn: 107609
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