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* R600: Use shared op optimization when checking cycle compatibilityVincent Lejeune2013-09-041-0/+2
| | | | llvm-svn: 189981
* R600: Non vector only instruction can be scheduled on trans unitVincent Lejeune2013-09-044-19/+60
| | | | llvm-svn: 189980
* R600: Use SchedModel enum for is{Trans,Vector}Only functionsVincent Lejeune2013-09-044-23/+19
| | | | llvm-svn: 189979
* ARM: Teach A15 SDOptimizer to properly handle D-reg by-lane.Jim Grosbach2013-09-041-0/+7
| | | | | | | | | | | | | These instructions, such as vmul.f32, require the second source operand to be in D0-D15 rather than the full D0-D31. When optimizing, make sure to account for that by constraining the register class of a replacement virtual register to be compatible with the virtual register(s) it's replacing. I've been unsuccessful in creating a non-fragile regression test. This issue was detected by the LLVM nightly test suite running on an A15 (Bullet). PR17093: http://llvm.org/bugs/show_bug.cgi?id=17093 llvm-svn: 189972
* Swift: Only build vldm/vstm with q register aligned register listsArnold Schwaighofer2013-09-041-1/+4
| | | | | | | | Unaligned vldm/vstm need more uops and therefore are slower in general on swift. radar://14522102 llvm-svn: 189961
* Fix scheduling for vldm/vstm instructions that load/store more than 32 bytes ↵Silviu Baranga2013-09-041-78/+54
| | | | | | on Cortex-A9. This also makes the existing code more compact. llvm-svn: 189958
* [Sparc] Fix an assertion failure while lowering fcmp on long double.Venkatraman Govindaraju2013-09-041-1/+1
| | | | | | | This assertion is triggered because an integer constant is created with wrong type. llvm-svn: 189948
* Inplement aarch64 neon instructions in AdvSIMD(shift). About 24 shift ↵Hao Liu2013-09-046-38/+805
| | | | | | | | | | instructions: sshr,ushr,ssra,usra,srshr,urshr,srsra,ursra,sri,shl,sli,sqshlu,sqshl,uqshl,shrn,sqrshrun,sqshrn,uqshr,sqrshrn,uqrshrn,sshll,ushll and 4 convert instructions: scvtf,ucvtf,fcvtzs,fcvtzu llvm-svn: 189925
* Add llvm namespace to llvm::next.Michael Gottesman2013-09-041-2/+2
| | | | llvm-svn: 189912
* Use llvm::next() instead of incrementing begin iterators of std::vector.Michael Gottesman2013-09-041-2/+2
| | | | | | | | | | Iterator of std::vector may be implemented as a raw pointer. In this case begin iterators are rvalues and cannot be incremented. For example, this is the case with STDCXX implementation of vector. Patch by Konstantin Tokarev <annulen@yandex.ru>. llvm-svn: 189911
* X86: Mark non-crashing report_fatal_errors() as such.Jim Grosbach2013-09-031-13/+19
| | | | | | | | | Previously, the clang crash handling code would kick in and give a crash report for these, even though they're not that sort of error. rdar://14882264 llvm-svn: 189878
* WIP: Refactor some code so that it can be called by more than just one ↵Bill Wendling2013-09-031-60/+71
| | | | | | method. No functionality change. llvm-svn: 189849
* Revert "Revert "ARM: Improve pattern for isel mul of vector by scalar.""Jim Grosbach2013-09-031-0/+11
| | | | | | | | | This reverts commit r189648. Fixes for the previously failing clang-side arm_neon_intrinsics test cases will be checked in separately. llvm-svn: 189841
* [SystemZ] Add support for TMHH, TMHL, TMLH and TMLLRichard Sandiford2013-09-032-8/+107
| | | | | | | | | For now this just handles simple comparisons of an ANDed value with zero. The CC value provides enough information to do any comparison for a 2-bit mask, and some nonzero comparisons with more populated masks, but that's all future work. llvm-svn: 189819
* [Sparc] Add support for soft long double (fp128).Venkatraman Govindaraju2013-09-033-18/+422
| | | | llvm-svn: 189780
* Add hadSideEffects=0 to some instructions.Craig Topper2013-09-031-1/+4
| | | | llvm-svn: 189779
* [Sparc] Implement spill and load for long double(f128) registers.Venkatraman Govindaraju2013-09-022-36/+123
| | | | llvm-svn: 189768
* ARM: Default to the Swift CPU when targeting armv7s/thumbv7s.Tilmann Scheller2013-09-021-2/+7
| | | | | | | | Test cases adjusted accordingly. This fixes rdar://14871821. llvm-svn: 189766
* Revert 189756 for now, it doesn't match what rdar://14871821 really wants.Tilmann Scheller2013-09-021-7/+2
| | | | | | What we really want is to enable Swift by default for *v7s triples (and there already seems to be some logic which attempts to do that). In that case the iOS version doesn't matter. llvm-svn: 189763
* ARM: Default to Swift when compiling for iOS 6 or later.Tilmann Scheller2013-09-021-2/+7
| | | | | | | | Test cases adjusted accordingly. This fixes rdar://14871821. llvm-svn: 189756
* Create BEXTR instructions for (and ((sra or srl) x, imm), (2**size - 1)). ↵Craig Topper2013-09-023-0/+29
| | | | | | Fixes PR17028. llvm-svn: 189742
* AVX-512: updated the list of high-latency instructions.Elena Demikhovsky2013-09-021-1/+23
| | | | llvm-svn: 189740
* AVX-512: gather-scatter tests; added foldable instructions;Elena Demikhovsky2013-09-021-1/+45
| | | | | | Specify GATHER/SCATTER as heavy instructions. llvm-svn: 189736
* AVX-512: Added GATHER and SCATTER instructions.Elena Demikhovsky2013-09-012-3/+285
| | | | llvm-svn: 189729
* Move everything depending on Object/MachOFormat.h over to Support/MachO.h.Charles Davis2013-09-017-208/+210
| | | | llvm-svn: 189728
* Make sure we don't generate stubs for any of these functions because theyReed Kotler2013-09-011-2/+21
| | | | | | | | | don't exist in libc. This is really not the right way to solve this problem; but it's not clear to me at this time exactly what is the right way. If we create stubs here, they will cause link errors because these functions do not exist in libc. llvm-svn: 189727
* Mark an unreachable code path with llvm_unreachable. Pacifies GCC.Benjamin Kramer2013-08-311-0/+1
| | | | llvm-svn: 189726
* [PowerPC] Fast-isel cleanup patch.Bill Schmidt2013-08-311-20/+37
| | | | | | | | | | | | | | | | | | | | Here are a few miscellaneous things to tidy up the PPC64 fast-isel implementation. I corrected a couple of commentary lapses, and added documentation of future opportunities. I also implemented TargetMaterializeAlloca, which I somehow forgot when I split up the original huge patch. Finally, I decided to delete SelectCmp. I hadn't previously hooked it in to TargetSelectInstruction(), and when I did I realized it wasn't serving any useful purpose. This is only useful for compares that don't feed a branch in the same block, and to handle that we would have to have logic to interpret i1 as a condition register. This could probably be done, but would require Unseemly Hackery, and honestly does not seem worth the hassle. This ends the current patch series. llvm-svn: 189715
* [PowerPC] Add integer truncation support to fast-isel.Bill Schmidt2013-08-301-0/+31
| | | | | | | | | | | | This is the last substantive patch I'm planning for fast-isel in the near future, adding fast selection of integer truncates. There are certainly more things that can be improved (many of which are called out in FIXMEs), but for now we are catching most of the important cases. I'll document some of the remaining work in a cleanup patch shortly. llvm-svn: 189706
* Correct partially defined variableBill Schmidt2013-08-301-1/+2
| | | | llvm-svn: 189705
* [PowerPC] Call support for fast-isel.Bill Schmidt2013-08-303-3/+338
| | | | | | | | | This patch adds fast-isel support for calls (but not intrinsic calls or varargs calls). It also removes a badly-formed assert. There are some new tests just for calls, and also for folding loads into arguments on calls to avoid extra extends. llvm-svn: 189701
* Build fixRichard Mitton2013-08-301-1/+1
| | | | llvm-svn: 189699
* Fixed a bug where diassembling an instruction that had a prefix would cause ↵Richard Mitton2013-08-301-7/+9
| | | | | | LLVM to identify a 1-byte instruction, but then upon querying it for that 1-byte instruction would cause an undefined opcode. llvm-svn: 189698
* Fix a problem with dual mips16/mips32 mode. When the underlying processorReed Kotler2013-08-305-5/+30
| | | | | | | | | | | | | has hard float, when you compile the mips32 code you have to make sure that it knows to compile any mips32 routines as hard float. I need to clean up the way mips16 hard float is specified but I need to first think through all the details. Mips16 always has a form of soft float, the difference being whether the underlying hardware has floating point. So it's not really necessary to pass the -soft-float to llvm since soft-float is always true for mips16 by virtue of the fact that it will not register floating point registers. By using this fact, I can simplify the way this is all handled. llvm-svn: 189690
* [PowerPC] Add handling for conversions to fast-isel.Bill Schmidt2013-08-304-0/+288
| | | | | | | | | Yet another chunk of fast-isel code. This one handles various conversions involving floating-point. (It also includes some miscellaneous handling throughout the back end for LWA_32 and LWAX_32 that should have been part of the load-store patch.) llvm-svn: 189677
* Checking commit access; removed one space added in previous test checkin by JimAndrey Churbanov2013-08-301-1/+1
| | | | llvm-svn: 189673
* X86: Add a description of the Intel Atom Silvermont CPU.Benjamin Kramer2013-08-301-0/+9
| | | | | | Currently this is just the atom model with SSE4.2 enabled. llvm-svn: 189669
* Fixup BZHI selection to remove an unneeded zero extension.Craig Topper2013-08-302-13/+15
| | | | llvm-svn: 189656
* Remove unused X86andn_flag node.Craig Topper2013-08-301-1/+0
| | | | llvm-svn: 189654
* Teach X86 backend to create BMI2 BZHI instructions from (and X, (add (shl 1, ↵Craig Topper2013-08-303-21/+64
| | | | | | Y), -1)). Fixes PR17038. llvm-svn: 189653
* Revert "ARM: Improve pattern for isel mul of vector by scalar."Michael Gottesman2013-08-301-11/+0
| | | | | | | | This reverts commit r189619. The commit was breaking the arm_neon_intrinsic test. llvm-svn: 189648
* mi-sched: Precompute a PressureDiff for each instruction, adjust for ↵Andrew Trick2013-08-302-6/+6
| | | | | | | | | | | | | liveness later. Created SUPressureDiffs array to hold the per node PDiff computed during DAG building. Added a getUpwardPressureDelta API that will soon replace the old one. Compute PressureDelta here from the precomputed PressureDiffs. Updating for liveness will come next. llvm-svn: 189640
* [PowerPC] Handle selection of compare instructions in fast-isel.Bill Schmidt2013-08-301-0/+18
| | | | | | | Mostly trivial patch adding support for compares. The meat of the work was added with the branch support. llvm-svn: 189639
* Remove bogus debug statement. Sheesh.Bill Schmidt2013-08-301-4/+2
| | | | llvm-svn: 189638
* [PowerPC] Add loads, stores, and related things to fast-isel.Bill Schmidt2013-08-303-7/+776
| | | | | | | | | | | | | | | | | | | | | | | | | This is the next big chunk of fast-isel code. The primary purpose is to implement selection of loads and stores, but there is a lot of drag-along to support this. The common code to analyze addresses for both loads and stores is substantial. It's also necessary to add the materialization code for global values. Related to load-store processing is the code to fold loads into integer extends, since otherwise we generate lots of redundant instructions. We also need to add some overrides to some FastEmit routines to ensure we don't assign GPR 0 to a virtual register when this would change the meaning of an instruction. I added handling selection of a few binary arithmetic instructions, to enable committing some test cases I wrote a while back. Finally, ap couple of miscellaneous changes: * I cleaned up some poor style from a previous patch in PPCISelLowering.cpp, pointed out by David Blaikie. * I enlarged the Addr.Offset field to avoid sign problems with 32-bit offsets. llvm-svn: 189636
* ARM: Improve pattern for isel mul of vector by scalar.Jim Grosbach2013-08-291-0/+11
| | | | | | | | | | | In addition to recognizing when the multiply's second argument is coming from an explicit VDUPLANE, also look for a plain scalar f32 reference and reference it via the corresponding vector lane. rdar://14870054 llvm-svn: 189619
* Clean up some usage of Triple. The base class has methods for determining ↵Cameron Esfahani2013-08-296-13/+10
| | | | | | if the target is iOS and Linux. llvm-svn: 189604
* AVX-512: added extend and truncate instructions.Elena Demikhovsky2013-08-294-29/+245
| | | | llvm-svn: 189580
* Add useAA() to TargetSubtargetInfoHal Finkel2013-08-291-0/+4
| | | | | | | | | | | | | There are several optional (off-by-default) features in CodeGen that can make use of alias analysis. These features are important for generating code for some kinds of cores (for example the (in-order) PPC A2 core). This adds a useAA() function to TargetSubtargetInfo to allow these features to be enabled by default on a per-subtarget basis. Here is the first use of this function: To control the default of the -enable-aa-sched-mi feature. llvm-svn: 189563
* The darwin integrated assembler for X86 in 64-bit mode is not rejectingKevin Enderby2013-08-291-1/+6
| | | | | | | | | | | | 32-bit absolute addressing in instructions likei this: mov $_f, %rsi which is not supported in 64-bit mode. rdar://8827134 llvm-svn: 189543
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