summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* [mips][FastISel] Use ternary operator to select opcode. NFCVasileios Kalintiris2015-10-071-8/+2
| | | | llvm-svn: 249594
* [mips][FastISel] Simple refactoring of MipsFastISel::emitLogicalOP(). NFC.Vasileios Kalintiris2015-10-071-13/+17
| | | | llvm-svn: 249580
* [AArch64] Fold a floating-point divide by power of two into fp conversion.Chad Rosier2015-10-071-0/+67
| | | | | | Part of http://reviews.llvm.org/D13442 llvm-svn: 249579
* AMDGPU: Fix missing implicit m0 uses on movrel instructionsMatt Arsenault2015-10-071-0/+7
| | | | llvm-svn: 249577
* [AArch64] Fold a floating-point multiply by power of two into fp conversion.Chad Rosier2015-10-071-0/+70
| | | | | | Part of http://reviews.llvm.org/D13442 llvm-svn: 249576
* [ARM] Promote helper function to SelectionDAG.Chad Rosier2015-10-071-34/+12
| | | | | | | | | I'll be using the function in a similar combine for AArch64. The helper was also improved to handle undef values. Part of http://reviews.llvm.org/D13442 llvm-svn: 249572
* Test commit access. Fixed comment to have correct input parameter name andKevin B. Smith2015-10-071-1/+1
| | | | | | period termination. llvm-svn: 249571
* [ARM] Use correct half-precision functions in EABI modeOliver Stannard2015-10-071-0/+8
| | | | | | | | | The ARM RTABI defines the half- to single-precision float conversion functions with an __aeabi prefix, but libgcc only has them with a __gnu prefix. Therefore we need to emit the __aeabi version when compiling with an eabi or eabihf triple, and the __gnu version with a gnueabi or gnueabihf triple. llvm-svn: 249565
* [ARM] Prevent PerformVDIVCombine from combining a vcvt/vdiv with 8 lanes.Chad Rosier2015-10-071-3/+4
| | | | | | This would result in a crash since the vcvt used does not support v8i32 types. llvm-svn: 249560
* [ARM][AArch64] Only lower to interleaved load/store if the target has NEONJeroen Ketema2015-10-072-10/+11
| | | | | | | | | Without an additional check for NEON, the compiler crashes during legalization of NEON ldN/stN. Differential Revision: http://reviews.llvm.org/D13508 llvm-svn: 249550
* Use non virtual destructors for sections.Rafael Espindola2015-10-072-21/+21
| | | | llvm-svn: 249548
* [ARM] Push more complex check down to reduce compile time. NFC.Chad Rosier2015-10-071-10/+10
| | | | llvm-svn: 249547
* Don't repeat names in comments and don't indent in namespaces. NFC.Rafael Espindola2015-10-071-3/+2
| | | | llvm-svn: 249546
* Revert: r249536 - Testing commit access with a trival whitespace change.Scott Egerton2015-10-071-1/+1
| | | | llvm-svn: 249537
* Testing commit access with a trival whitespace change.Scott Egerton2015-10-071-1/+1
| | | | llvm-svn: 249536
* [X86] Emit .cfi_escape GNU_ARGS_SIZE when adjusting the stack before callsMichael Kuperstein2015-10-071-2/+19
| | | | | | | | | | | | When outgoing function arguments are passed using push instructions, and EH is enabled, we may need to indicate to the stack unwinder that the stack pointer was adjusted before the call. This should fix the exception handling issues in PR24792. Differential Revision: http://reviews.llvm.org/D13132 llvm-svn: 249522
* AVX512: Change encoding of vpshuflw and vpshufhw instructions. Implement WIG ↵Igor Breger2015-10-071-3/+2
| | | | | | | | | | as W0 and not W1, like all other instruction have been implemented. Add encoding tests. Differential Revision: http://reviews.llvm.org/D13471 llvm-svn: 249521
* AMDGPU: Add comment for VOP2b operand classMatt Arsenault2015-10-071-0/+5
| | | | | | | | Because of the constant bus requirement, it is never legal to use a literal constant for these instructions despite the encoding allowing it. This was already doing the right thing, but note why. llvm-svn: 249500
* AMDGPU: Properly register passesMatt Arsenault2015-10-071-2/+2
| | | | llvm-svn: 249495
* AMDGPU: Use explicit register size indirect pseudosMatt Arsenault2015-10-073-17/+28
| | | | | | | | | | | | | | | | | This stops using an unknown reg class operand. Currently build_vector selection has a broken looking check where it tries to use a VGPR reg class and an SGPR one if it sees an SGPR use. With the source operand has an explicit VGPR class, illegal copies will be inserted that SIFixSGPRCopies will take care of normally later, which will allow removing the weird check of build_vector users. Without this, when removed v_movrels_b32 would still be emitted even though all of the values were only stored in SGPRs. llvm-svn: 249494
* AMDGPU: Remove inferRegClassFromUses / inferRegClassFromDefsMatt Arsenault2015-10-071-70/+0
| | | | | | | | | I'm not sure why this would be necessary, and no tests fail with them removed. Looking at the uses is suspect as well because the use reg classes will likely change when the users are moved as a result of moving this instruction. llvm-svn: 249493
* Fix Clang-tidy modernize-use-nullptr warnings in source directories and ↵Hans Wennborg2015-10-061-4/+5
| | | | | | | | | | generated files; other minor cleanups. Patch by Eugene Zelenko! Differential Revision: http://reviews.llvm.org/D13321 llvm-svn: 249482
* AMDGPU/SI: Remove calling convention assertion from LowerFormalArguments()Tom Stellard2015-10-061-1/+1
| | | | | | | | | | | | | | Summary: We currently ignore the calling convention, so there is no real reason to assert on the calling convention of functions. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13367 llvm-svn: 249468
* [ARM] Minor refactoring. NFC.Chad Rosier2015-10-061-2/+4
| | | | llvm-svn: 249465
* [ARM] Minor refactoring. NFC.Chad Rosier2015-10-061-8/+10
| | | | llvm-svn: 249464
* [ARM] Minor refactoring. NFC.Chad Rosier2015-10-061-9/+8
| | | | llvm-svn: 249463
* [WinEH] Recognize CoreCLR personality functionJoseph Tremoulet2015-10-062-6/+6
| | | | | | | | | | | | | | | Summary: - Add CoreCLR to if/else ladders and switches as appropriate. - Rename isMSVCEHPersonality to isFuncletEHPersonality to better reflect what it captures. Reviewers: majnemer, andrew.w.kaylor, rnk Subscribers: pgavlin, AndyAyers, llvm-commits Differential Revision: http://reviews.llvm.org/D13449 llvm-svn: 249455
* [ARM] Minor refactoring to improve readability. NFC.Chad Rosier2015-10-061-13/+14
| | | | llvm-svn: 249454
* [Hexagon] Remove ZeroOrMore from option flagsKrzysztof Parzyszek2015-10-061-4/+3
| | | | llvm-svn: 249438
* AMDGPU/SI: Add 64-bit versions of v_nop and v_clrexcpTom Stellard2015-10-065-25/+56
| | | | | | | | | | | | | | Summary: The assembly printing of these is still missing the encoding size suffix, but this will be fixed in a later commit. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13436 llvm-svn: 249424
* [Hexagon] Add an early if-conversion passKrzysztof Parzyszek2015-10-064-17/+1149
| | | | llvm-svn: 249423
* [mips][microMIPS] Fix an issue with selecting sqrt instruction in LLVM backendDaniel Sanders2015-10-061-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This fixes 7 tests during fast LLVM test-suite run: * MultiSource/Benchmarks/McCat/18-imp/imp * MultiSource/Applications/oggenc/oggenc * MultiSource/Benchmarks/MallocBench/gs/gs * MultiSource/Benchmarks/MiBench/automotive-susan/automotive-susan * MultiSource/Benchmarks/VersaBench/beamformer/beamformer * MultiSource/Benchmarks/MiBench/consumer-lame/consumer-lame * MultiSource/Benchmarks/Bullet/bullet Error message was in the form of: fatal error: error in backend: Cannot select: 0x95c3288: f32 = fsqrt 0x95c0190 [ORD=9] [ID=18] 0x95c0190: f32 = fadd 0x95bef30, 0x95c4d00 [ORD=8] [ID=17] 0x95bef30: f32 = fmul 0x95c4988, 0x95c4988 [ORD=5] [ID=16] ... There was problem with selecting sqrt instruction in LLVM backend. To fix the issue changes are made in TableGen definition for sqrt instruction in MipsInstrFPU.td and new test file sqrt.ll is added to LLVM regression tests. Patch by Zlatko Buljan Reviewers: zoran.jovanovic, hvarga, dsanders Subscribers: llvm-commits, petarj Differential Revision: http://reviews.llvm.org/D13235 llvm-svn: 249416
* Revert r249123 - [mips][microMIPS] Fix an issue with selecting sqrt ↵Daniel Sanders2015-10-061-2/+5
| | | | | | | | instruction in LLVM backend The author was not credited and most of the commit message is missing. Will re-commit with this fixed. llvm-svn: 249415
* [bpf] Avoid extra pointer arithmetic for stack accessAlexei Starovoitov2015-10-063-7/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | For the program like below struct key_t { int pid; char name[16]; }; extern void test1(char *); int test() { struct key_t key = {}; test1(key.name); return 0; } For key.name, the llc/bpf may generate the below code: R1 = R10 // R10 is the frame pointer R1 += -24 // framepointer adjustment R1 |= 4 // R1 is then used as the first parameter of test1 OR operation is not recognized by in-kernel verifier. This patch introduces an intermediate FI_ri instruction and generates the following code that can be properly verified: R1 = R10 R1 += -20 Patch by Yonghong Song <yhs@plumgrid.com> llvm-svn: 249371
* [X86] Teach constant hoisting that ANDs with 64-bit immediates in the range ↵Craig Topper2015-10-061-1/+7
| | | | | | | | 0x80000000-0xffffffff can be handled cheaply and don't need to be hoisted. Most importantly, this keeps constant hoisting from preventing instruction selections ability to turn an AND with 0xffffffff into a move into a 32-bit subregister. llvm-svn: 249370
* [X86] Remove unnecessary AddComplexity directive. The instruction is already ↵Craig Topper2015-10-061-1/+0
| | | | | | wrapped in the equivalent earlier. NFC llvm-svn: 249369
* [WebAssembly] Switch to a more traditional assembly syntaxDan Gohman2015-10-064-144/+113
| | | | | | | | | | | This new syntax is built around putting each instruction on its own line in a "mnemonic op, op, op" like syntax. It also uses conventional data section directives like ".byte" and so on rather than requiring everything to be in hierarchical S-expression format. This is a more natural syntax for a ".s" file format from the perspective of LLVM MC and related tools, while remaining easy to translate into other forms as needed. llvm-svn: 249364
* [WinEH] Update CATCHRET's operand to match its successorDavid Majnemer2015-10-051-0/+1
| | | | | | | | | | | | The CATCHRET operand did not match the MachineFunction's CFG. This mismatch happened because FrameLowering created a new MachineBasicBlock and updated the CFG but forgot to update the CATCHRET operand. Let's make sure this doesn't happen again by strengthing the funclet membership analysis: it can now reason about the membership of all basic blocks, not just those inside of funclets. llvm-svn: 249344
* AMDGPU/SI: Add a helper for creating aliases for the _e32 instructionsTom Stellard2015-10-051-11/+49
| | | | | | | | | | | | | | | | | | Summary: We are currently only using these aliases for VOPC instructions, but this helper will make it easier to use them everywhere. These aliases allow for the automatic matching of instructions with forced 32-bit encoding. Eventually, we should be able to remove the custom C++ logic we have for this in the assembler. Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13396 llvm-svn: 249330
* [ARM] Modify codegen for memcpy intrinsic to prefer LDM/STM.Scott Douglass2015-10-058-30/+166
| | | | | | | | | | | | | | | | | | | | | | | | | | | We were previously codegen'ing memcpy as regular load/store operations and hoping that the register allocator would allocate registers in ascending order so that we could apply an LDM/STM combine after register allocation. According to the commit that first introduced this code (r37179), we planned to teach the register allocator to allocate the registers in ascending order. This never got implemented, and up to now we've been stuck with very poor codegen. A much simpler approach for achieving better codegen is to create MEMCPY pseudo instructions, attach scratch virtual registers to them and then, post register allocation, expand the MEMCPYs into LDM/STM pairs using the scratch registers. The register allocator will have picked arbitrary registers which we sort when expanding the MEMCPY. This approach also avoids the need to repeatedly calculate offsets which ultimately ought to be eliminated pre-RA in order to decrease register pressure. Fixes PR9199 and PR23768. [This is based on Peter Collingbourne's r238473 which was reverted.] Differential Revision: http://reviews.llvm.org/D13239 Change-Id: I727543c2e94136e0f80b8e22d5642d7b9ee5b458 Author: Peter Collingbourne <peter@pcc.me.uk> llvm-svn: 249322
* [mips][microMIPS] Implement JALRC16, JRCADDIUSP and JRC16 instructionsZoran Jovanovic2015-10-055-5/+82
| | | | | | Differential Revision: http://reviews.llvm.org/D11219 llvm-svn: 249317
* [MC layer][AArch64] llvm-mc accepts 4-bit immediate values forAlexandros Lamprineas2015-10-055-13/+87
| | | | | | | | | "msr pan, #imm", while only 1-bit immediate values should be valid. Changed encoding and decoding for msr pstate instructions. Differential Revision: http://reviews.llvm.org/D13011 llvm-svn: 249313
* [mips] Changed the way symbols are handled in dla and la instructions to ↵Daniel Sanders2015-10-051-12/+9
| | | | | | | | | | | | | | | | | | | | | allow simple expressions. Summary: An instruction like "(d)la $5, symbol+8" previously would have crashed the assembler as it contains an expression. This is now fixed. A few tests cases have also been changed to reflect these changes, however these should only be syntax changes. Some new test cases have also been added. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12760 llvm-svn: 249311
* Fix pr24486.Rafael Espindola2015-10-058-13/+13
| | | | | | | | | | | | | | | | | | This extends the work done in r233995 so that now getFragment (in addition to getSection) also works for variable symbols. With that the existing logic to decide if a-b can be computed works even if a or b are variables. Given that, the expression evaluation can avoid expanding variables as aggressively and that in turn lets the relocation code see the original variable. In order for this to work with the asm streamer, there is now a dummy fragment per section. It is used to assign a section to a symbol when no other fragment exists. This patch is a joint work by Maxim Ostapenko andy myself. llvm-svn: 249303
* [SPARCv9] Add support for the rdpr/wrpr instructions.Joerg Sonnenberger2015-10-044-0/+131
| | | | llvm-svn: 249262
* AVX512: Implemented encoding and intrinsics for VPERMILPS/PD instructions.Igor Breger2015-10-044-61/+102
| | | | | | | | Added tests for intrinsics and encoding. Differential Revision: http://reviews.llvm.org/D12690 llvm-svn: 249261
* Fix typo in READMEJeroen Ketema2015-10-041-1/+1
| | | | llvm-svn: 249253
* [X86] Lower SEXTLOAD using SIGN_EXTEND_VECTOR_INREG. NCI.Simon Pilgrim2015-10-031-22/+5
| | | | | | The custom lowering in LowerExtendedLoad is doing the equivalent shuffle, so make use of existing lowering code to reduce duplication. llvm-svn: 249243
* [WebAssembly] Implement the remaining conversion operations.Dan Gohman2015-10-031-31/+54
| | | | | | | This is a temporary assembly syntax that will likely evolve along with broader upcoming syntax changes. llvm-svn: 249225
* AMDGPU/SI: Remove unused tablegen multiclassTom Stellard2015-10-031-16/+0
| | | | | | | | | | Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13395 llvm-svn: 249221
OpenPOWER on IntegriCloud