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* Size reducing SP adjusting t2ADDri needs to check predication.Jim Grosbach2011-06-301-1/+4
| | | | | | | tADDrSPi is not predicable, so we can't size-reduce a t2ADDri to it if the predicate is anything other than "always." llvm-svn: 134130
* Fix ARMSubtarget feature parsing.Evan Cheng2011-06-301-10/+7
| | | | llvm-svn: 134129
* Fix the ridiculous SubtargetFeatures API where it implicitly expects CPU name toEvan Cheng2011-06-3056-145/+210
| | | | | | | | | | be the first encoded as the first feature. It then uses the CPU name to look up features / scheduling itineray even though clients know full well the CPU name being used to query these properties. The fix is to just have the clients explictly pass the CPU name! llvm-svn: 134127
* Recognize the xstorerng alias for VIA PadLock's xstore instruction.Joerg Sonnenberger2011-06-301-0/+2
| | | | llvm-svn: 134126
* Make sure we use the correct register class here since we'll need toEric Christopher2011-06-301-1/+2
| | | | | | care about spill values. llvm-svn: 134122
* Fix a small thinko for constant i64 lock/orq optimization where weEric Christopher2011-06-301-2/+4
| | | | | | | | we didn't have an opcode for 64-bit constant or expressions. Fixes rdar://9692967 llvm-svn: 134121
* Remove redundant Thumb2 ADD/SUB SP instruction definitions.Jim Grosbach2011-06-296-113/+55
| | | | | | | | | | Unlike Thumb1, Thumb2 does not have dedicated encodings for adjusting the stack pointer. It can just use the normal add-register-immediate encoding since it can use all registers as a source, not just R0-R7. The extra instruction definitions are just duplicates of the normal instructions with the (not well enforced) constraint that the source register was SP. llvm-svn: 134114
* Always adjust the stack pointer immediately after the call.Jakob Stoklund Olesen2011-06-291-0/+7
| | | | | | | | | | | | | | | | | | | Some x86-32 calls pop values off the stack, and we need to readjust the stack pointer after the call. This happens when ADJCALLSTACKUP is eliminated. It could happen that spill code was inserted between the CALL and ADJCALLSTACKUP instructions, and we would compute wrong stack pointer offsets for those frame index references. Fix this by inserting the stack pointer adjustment immediately after the call instead of where the ADJCALLSTACKUP instruction was erased. I don't have a test case since we don't currently insert code in that position. We will soon, though. I am testing a regalloc patch that didn't work on Linux because of this. llvm-svn: 134113
* In the ARM global merging pass, allow extraneous alignment specifiers. This passCameron Zwarich2011-06-291-2/+4
| | | | | | | | already makes the assumption, which is correct on ARM, that a type's alignment is less than its alloc size. This improves codegen with Clang (which inserts a lot of extraneous alignment specifiers) and fixes <rdar://problem/9695089>. llvm-svn: 134106
* Remove getRegClassForInlineAsmConstraint from the ARM port.Eric Christopher2011-06-292-59/+15
| | | | | | Part of rdar://9643582 llvm-svn: 134095
* Remove todo.Eric Christopher2011-06-291-2/+0
| | | | llvm-svn: 134094
* Refactor away tSpill and tRestore pseudos in ARM backend.Jim Grosbach2011-06-295-36/+8
| | | | | | | The tSpill and tRestore instructions are just copies of the tSTRspi and tLDRspi instructions, respectively. Just use those directly instead. llvm-svn: 134092
* Add a TODO for the Alpha port inline asm constraints.Eric Christopher2011-06-291-0/+2
| | | | llvm-svn: 134089
* Move Alpha from getRegClassForInlineAsmConstraint toEric Christopher2011-06-292-32/+14
| | | | | | | | getRegForInlineAsmConstraint. Part of rdar://9643582 llvm-svn: 134088
* Update comment for getRegForInlineAsmConstraint for Mips.Eric Christopher2011-06-291-3/+3
| | | | llvm-svn: 134087
* Move the Blackfin port away from getRegClassForInlineAsmConstraint byEric Christopher2011-06-293-29/+22
| | | | | | | | creating a few specific register classes. Part of rdar://9643582 llvm-svn: 134086
* Remove getRegClassForInlineAsmConstraint from MBlaze. Add a TODO commentEric Christopher2011-06-292-33/+7
| | | | | | | | for the port. Part of rdar://9643582 llvm-svn: 134085
* Remove getRegClassForInlineAsmConstraint for Mips.Eric Christopher2011-06-292-48/+3
| | | | | | Part of rdar://9643582 llvm-svn: 134084
* Remove getRegClassForInlineAsmConstraint from sparc.Eric Christopher2011-06-292-24/+0
| | | | | | Part of rdar://9643582 llvm-svn: 134083
* Move XCore from getRegClassForInlineAsmConstraint toEric Christopher2011-06-292-17/+14
| | | | | | | | getRegForInlineAsmConstraint. Part of rdar://9643582 llvm-svn: 134080
* Use getRegForInlineAsmConstraint instead of custom defining regclassesEric Christopher2011-06-292-56/+24
| | | | | | | | via vectors. Part of rdar://9643582 llvm-svn: 134079
* Fix CMake build.NAKAMURA Takumi2011-06-291-1/+0
| | | | llvm-svn: 134055
* Sink SubtargetFeature and TargetInstrItineraries (renamed ↵Evan Cheng2011-06-298-398/+8
| | | | | | MCInstrItineraries) into MC. llvm-svn: 134049
* Move CallFrameSetupOpcode and CallFrameDestroyOpcode to TargetInstrInfo.Evan Cheng2011-06-2828-59/+58
| | | | llvm-svn: 134030
* Hide more details in tablegen generated MCRegisterInfo ctor function.Evan Cheng2011-06-2813-25/+13
| | | | llvm-svn: 134027
* Add MCInstrInfo registeration machinery.Evan Cheng2011-06-281-0/+6
| | | | llvm-svn: 134026
* Merge XXXGenRegisterNames.inc into XXXGenRegisterInfo.incEvan Cheng2011-06-2862-87/+112
| | | | llvm-svn: 134024
* - Rename TargetInstrDesc, TargetOperandInfo to MCInstrDesc and MCOperandInfo andEvan Cheng2011-06-2838-470/+469
| | | | | | | | sink them into MC layer. - Added MCInstrInfo, which captures the tablegen generated static data. Chang TargetInstrInfo so it's based off MCInstrInfo. llvm-svn: 134021
* Clean up the handling of the x87 fp stack to make it more robust.Jakob Stoklund Olesen2011-06-286-227/+362
| | | | | | | | | | | | | | | | | | | | Drop the FpMov instructions, use plain COPY instead. Drop the FpSET/GET instruction for accessing fixed stack positions. Instead use normal COPY to/from ST registers around inline assembly, and provide a single new FpPOP_RETVAL instruction that can access the return value(s) from a call. This is still necessary since you cannot tell from the CALL instruction alone if it returns anything on the FP stack. Teach fast isel to use this. This provides a much more robust way of handling fixed stack registers - we can tolerate arbitrary FP stack instructions inserted around calls and inline assembly. Live range splitting could sometimes break x87 code by inserting spill code in unfortunate places. As a bonus we handle floating point inline assembly correctly now. llvm-svn: 134018
* Remove warning: 'c0' may be used uninitialized in this function.Chad Rosier2011-06-281-1/+2
| | | | llvm-svn: 134014
* Implement ISD::VAARG lowering on PPC32.Roman Divacky2011-06-281-5/+123
| | | | llvm-svn: 134005
* Fix cmake build.Rafael Espindola2011-06-281-1/+1
| | | | llvm-svn: 133989
* ARM Thumb2 asm syntax optional destination operand for binary operators.Jim Grosbach2011-06-281-9/+29
| | | | | | | | | | | | | When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: and r1, #ff and r1, r1, #ff rdar://9672867 llvm-svn: 133973
* ARM Assembly support for Thumb mov-immediate.Jim Grosbach2011-06-273-4/+40
| | | | | | | | | | | Correctly parse the forms of the Thumb mov-immediate instruction: 1. 8-bit immediate 0-255. 2. 12-bit shifted-immediate. The 16-bit immediate "movw" form is also legal with just a "mov" mnemonic, but is not yet supported. More parser logic necessary there due to fixups. llvm-svn: 133966
* ARM Asm parsing of Thumb2 move immediate.Jim Grosbach2011-06-271-2/+3
| | | | | | | Thumb2 MOV mnemonic can accept both cc_out and predication. We don't (yet) encode the instruction properly, but this gets the parsing part. llvm-svn: 133945
* More refactoring. Move getRegClass from TargetOperandInfo to TargetInstrInfo.Evan Cheng2011-06-276-29/+28
| | | | llvm-svn: 133944
* Add exception necessitated by 133938.Jim Grosbach2011-06-271-1/+1
| | | | llvm-svn: 133939
* ARM assembly carry set/clear condition code aliases for 'hi/lo'Jim Grosbach2011-06-271-0/+2
| | | | llvm-svn: 133938
* ARM assembler support for ldmfd/stmfd mnemonics.Jim Grosbach2011-06-271-0/+2
| | | | llvm-svn: 133936
* ARM assembler support for vpush/vpop.Jim Grosbach2011-06-271-0/+9
| | | | | | | | | Add aliases for the vpush/vpop mnemonics to the VFP load/store multiple writeback instructions w/ SP as the base pointer. rdar://9683231 llvm-svn: 133932
* ARM Assembly syntax support for arithmetic implied dest operand.Jim Grosbach2011-06-271-7/+25
| | | | | | | | | | | | | When the destination operand is the same as the first source register operand for arithmetic instructions, the destination operand may be omitted. For example, the following two instructions are equivalent: sub r2, r2, #6 sub r2, #6 rdar://9682597 llvm-svn: 133925
* Merge XXXGenRegisterDesc.inc XXXGenRegisterNames.inc XXXGenRegisterInfo.h.incEvan Cheng2011-06-2768-121/+130
| | | | | | into XXXGenRegisterInfo.inc. llvm-svn: 133922
* Grow the X86FloatingPoint register map to hold 16 registers.Jakob Stoklund Olesen2011-06-271-5/+15
| | | | | | | This allows for more live scratch registers which is needed to handle live ST registers before return and inline asm instructions. llvm-svn: 133903
* Replace dyn_cast<> with cast<> since the cast is already guarded by the ↵Chad Rosier2011-06-251-1/+1
| | | | | | necessary check. llvm-svn: 133874
* PTX: Reverting implementation of i8.Dan Bailey2011-06-257-296/+73
| | | | | | | | The .b8 operations in PTX are far more limiting than I first thought. The mov operation isn't even supported, so there's no way of converting a .pred value into a .b8 without going via .b16, which is not sensible. An improved implementation needs to use the fact that loads and stores automatically extend and truncate to implement support for EXTLOAD and TRUNCSTORE in order to correctly support boolean values. llvm-svn: 133873
* Enable tail call optimization in the presence of a byval (x86-32 and x86-64).Chad Rosier2011-06-251-0/+4
| | | | | | <rdar://problem/9483883> llvm-svn: 133858
* Unbreak CMake buildDouglas Gregor2011-06-251-0/+2
| | | | llvm-svn: 133853
* Add include guard.Evan Cheng2011-06-241-0/+5
| | | | llvm-svn: 133847
* Rename TargetDesc to MCTargetDescEvan Cheng2011-06-246-4/+3
| | | | llvm-svn: 133846
* Refactor MachO relocation generaration into the Target directories.Jim Grosbach2011-06-243-0/+885
| | | | | | | | | Move the target-specific RecordRelocation logic out of the generic MC MachObjectWriter and into the target-specific object writers. This allows nuking quite a bit of target knowledge from the supposedly target-independent bits in lib/MC. llvm-svn: 133844
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