summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* add some long-overdue enums to refer to the parts of the 5-operandChris Lattner2010-07-086-44/+56
| | | | | | X86 memory operand. llvm-svn: 107925
* Remember the VR64 register classJakob Stoklund Olesen2010-07-081-0/+2
| | | | llvm-svn: 107920
* Rework segment prefix emission code to handle segmentsChris Lattner2010-07-081-47/+41
| | | | | | | | | | | | in memory operands at the same type as hard coded segments. This fixes problems where we'd emit the segment override after the REX prefix on instructions like: mov %gs:(%rdi), %rax This fixes rdar://8127102. I have several cleanup patches coming next. llvm-svn: 107917
* introduce a new X86II::getMemoryOperandNo method, whichChris Lattner2010-07-081-12/+71
| | | | | | | | | returns the start of the memory operand for an instruction. Introduce a new "X86AddrSegment" enum to reduce # magic numbers referring to X86 memory operand layout. llvm-svn: 107916
* Switch SPU calling convention (function arguments) Kalle Raiskila2010-07-084-118/+52
| | | | | | to a Tablegen implementation. llvm-svn: 107913
* Check for FiniteOnlyFPMath as well.Evan Cheng2010-07-081-1/+1
| | | | llvm-svn: 107904
* Teach the x86 floating point stackifier to handle COPY instructions.Jakob Stoklund Olesen2010-07-081-1/+36
| | | | | | | | | | | This pass runs before COPY instructions are passed to copyPhysReg, so we simply translate COPY to the proper pseudo instruction. Note that copyPhysReg does not handle floating point stack copies. Once COPY is used everywhere, this can be cleaned up a bit, and most of the pseudo instructions can be removed. llvm-svn: 107899
* Implement X86InstrInfo::copyPhysRegJakob Stoklund Olesen2010-07-082-0/+64
| | | | llvm-svn: 107898
* The NEONPreAllocPass should never have to assign fixed registers anymore.Bob Wilson2010-07-081-34/+1
| | | | | | This pass can go away entirely soon. llvm-svn: 107892
* For big-endian systems, VLD2/VST2 with 32-bit vector elements will swap theBob Wilson2010-07-081-2/+2
| | | | | | | words within the 64-bit D registers. Use VLD1/VST1 with 64-bit elements instead. llvm-svn: 107890
* Clean up a comment.Bob Wilson2010-07-081-5/+5
| | | | llvm-svn: 107882
* Convert EXTRACT_SUBREG to COPY when emitting machine instrs.Jakob Stoklund Olesen2010-07-083-10/+8
| | | | | | | | | EXTRACT_SUBREG no longer appears as a machine instruction. Use COPY instead. Add isCopy() checks in many places using isMoveInstr() and isExtractSubreg(). The isMoveInstr hook will be removed later. llvm-svn: 107879
* Remove references to INSERT_SUBREG after de-SSA.Jakob Stoklund Olesen2010-07-081-8/+6
| | | | | | | Fix X86InstrInfo::convertToThreeAddressWithLEA to generate COPY instead of INSERT_SUBREG. llvm-svn: 107878
* Teach instcombine to transformBenjamin Kramer2010-07-081-11/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | (X >s -1) ? C1 : C2 and (X <s 0) ? C2 : C1 into ((X >>s 31) & (C2 - C1)) + C1, avoiding the conditional. This optimization could be extended to take non-const C1 and C2 but we better stay conservative to avoid code size bloat for now. for int sel(int n) { return n >= 0 ? 60 : 100; } we now generate sarl $31, %edi andl $40, %edi leal 60(%rdi), %eax instead of testl %edi, %edi movl $60, %ecx movl $100, %eax cmovnsl %ecx, %eax llvm-svn: 107866
* A slight reworking of the custom patterns for x86-64 tpoff codegen andEric Christopher2010-07-081-9/+11
| | | | | | | | correct the testcase for valid assembly. Needs more tests. llvm-svn: 107860
* r107852 is only safe with -enable-unsafe-fp-math to account for +0.0 == -0.0.Evan Cheng2010-07-081-3/+5
| | | | llvm-svn: 107856
* Optimize some vfp comparisons to integer ones. This patch implements the ↵Evan Cheng2010-07-082-10/+48
| | | | | | | | | | | | | | | | | | | | | | | | simplest case when the following conditions are met: 1. The arguments are f32. 2. The arguments are loads and they have no uses other than the comparison. 3. The comparison code is EQ or NE. e.g. vldr.32 s0, [r1] vldr.32 s1, [r0] vcmpe.f32 s1, s0 vmrs apsr_nzcv, fpscr beq LBB0_2 => ldr r1, [r1] ldr r0, [r0] cmp r0, r1 beq LBB0_2 More complicated cases will be implemented in subsequent patches. llvm-svn: 107852
* Changes to ARM tail calls, mostly cosmetic.Dale Johannesen2010-07-083-8/+20
| | | | | | | | | Add explicit testcases for tail calls within the same module. Duplicate some code to humor those who think .w doesn't apply on ARM. Leave this disabled on Thumb1, and add some comments explaining why it's hard and won't gain much. llvm-svn: 107851
* Revert 107840 107839 107813 107804 107800 107797 107791.Dan Gohman2010-07-085-193/+69
| | | | | | Debug info intrinsics win for now. llvm-svn: 107850
* fix copies to/from GR8_ABCD_H even moreJakob Stoklund Olesen2010-07-071-1/+3
| | | | llvm-svn: 107832
* grammarJim Grosbach2010-07-071-1/+1
| | | | llvm-svn: 107831
* Handle cases where the post-RA scheduler may move instructions between theJim Grosbach2010-07-071-6/+21
| | | | | | | | | address calculation instructions leading up to a jump table when we're trying to convert them into a TB[H] instruction in Thumb2. This realistically shouldn't happen much, if at all, for well formed inputs, but it's more correct to handle it. rdar://7387682 llvm-svn: 107830
* finish up support for callw: PR7195Chris Lattner2010-07-071-1/+1
| | | | llvm-svn: 107826
* Implement the major chunk of PR7195: support for 'callw'Chris Lattner2010-07-076-11/+36
| | | | | | | in the integrated assembler. Still some discussion to be done. llvm-svn: 107825
* Add more assembly opcodes for SSE compare instructionsBruno Cardoso Lopes2010-07-071-8/+32
| | | | llvm-svn: 107823
* Move getExtLoad() and (some) getLoad() DebugLoc argument after EVT argument ↵Evan Cheng2010-07-076-9/+9
| | | | | | for consistency sake. llvm-svn: 107820
* Print undefined/unknown debug value as "undef".Devang Patel2010-07-071-1/+6
| | | | llvm-svn: 107818
* grammar and trailing whitespaceJim Grosbach2010-07-071-6/+6
| | | | llvm-svn: 107811
* Allow copies between GR8_ABCD_L and GR8_ABCD_H.Jakob Stoklund Olesen2010-07-071-0/+3
| | | | | | This fixes PR7540. llvm-svn: 107809
* Implement bottom-up fast-isel. This has the advantage of not requiringDan Gohman2010-07-071-22/+42
| | | | | | a separate DCE pass over MachineInstrs. llvm-svn: 107804
* Add X86FastISel support for return statements. This entails refactoringDan Gohman2010-07-075-12/+78
| | | | | | | a bunch of stuff, to allow the target-independent calling convention logic to be employed. llvm-svn: 107800
* Add AVX AES instructionsBruno Cardoso Lopes2010-07-071-26/+70
| | | | llvm-svn: 107798
* Give FunctionLoweringInfo an MBB member, avoiding the need to pass itDan Gohman2010-07-071-57/+95
| | | | | | | | around everywhere, and also give it an InsertPt member, to enable isel to operate at an arbitrary position within a block, rather than just appending to a block. llvm-svn: 107791
* Simplify FastISel's constructor by giving it a FunctionLoweringInfoDan Gohman2010-07-073-71/+19
| | | | | | | | | instance, rather than pointers to all of FunctionLoweringInfo's members. This eliminates an NDEBUG ABI sensitivity. llvm-svn: 107789
* Split the SDValue out of OutputArg so that SelectionDAG-independentDan Gohman2010-07-0726-53/+125
| | | | | | code can do calling-convention queries. This obviates OutputArgReg. llvm-svn: 107786
* Add AVX SSE4.2 instructionsBruno Cardoso Lopes2010-07-071-114/+179
| | | | llvm-svn: 107752
* Use only one multiclass to pinsrq instructionsBruno Cardoso Lopes2010-07-072-38/+20
| | | | llvm-svn: 107750
* Now that almost all SSE4.1 AVX instructions are added, move code around to ↵Bruno Cardoso Lopes2010-07-072-361/+374
| | | | | | more appropriate sections. No functionality changes llvm-svn: 107749
* Add AVX SSE4.1 insertps, ptest and movntdqa instructionsBruno Cardoso Lopes2010-07-071-18/+39
| | | | llvm-svn: 107747
* Add AVX SSE4.1 extractps and pinsr instructionsBruno Cardoso Lopes2010-07-071-35/+67
| | | | llvm-svn: 107746
* Also use REG_SEQUENCE for VTBX instructions.Bob Wilson2010-07-072-24/+30
| | | | llvm-svn: 107743
* Mark eh.sjlj.set/longjmp custom lowerings as Darwin-only since that's whereJim Grosbach2010-07-071-2/+4
| | | | | | they've been tested to work. llvm-svn: 107742
* Add AVX SSE4.1 Extract Integer instructionsBruno Cardoso Lopes2010-07-071-0/+11
| | | | llvm-svn: 107740
* By default, the eh.sjlj.setjmp/longjmp intrinsics should just do nothing ratherJim Grosbach2010-07-061-0/+2
| | | | | | | than assuming a target will custom lower them. Targets which do so should exlicitly mark them as having custom lowerings. PR7454. llvm-svn: 107734
* Use REG_SEQUENCE nodes to make the table registers for VTBL instructions beBob Wilson2010-07-062-10/+61
| | | | | | allocated to consecutive registers. llvm-svn: 107730
* Accept RIP-relative symbols with 'i' constraint, andDale Johannesen2010-07-062-2/+3
| | | | | | | print the (%rip) only if the 'a' modifier is present. PR 7528. llvm-svn: 107727
* Track defs for all aliases in NEONMoveFix.Jakob Stoklund Olesen2010-07-061-2/+2
| | | | | | | This means that an instruction defining an S register will affect the domain of the parent D register. llvm-svn: 107725
* Add the rest of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-061-0/+17
| | | | llvm-svn: 107723
* Add part of AVX SSE4.1 packed move with sign/zero extend instructionsBruno Cardoso Lopes2010-07-061-0/+15
| | | | llvm-svn: 107720
* Fix comment from previous patchBruno Cardoso Lopes2010-07-061-1/+1
| | | | llvm-svn: 107717
OpenPOWER on IntegriCloud