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* Added a size field to the stack map record to handle subregister spills.Andrew Trick2013-11-173-12/+41
| | | | | | | | Implementing this on bigendian platforms could get strange. I added a target hook, getStackSlotRange, per Jakob's recommendation to make this as explicit as possible. llvm-svn: 194942
* The WebKit_JS CC preserves the same registers as the C CC.Juergen Ributzka2013-11-161-0/+1
| | | | llvm-svn: 194936
* R600: Make dot_4 instructions predicableVincent Lejeune2013-11-161-0/+19
| | | | llvm-svn: 194927
* X86: Encode the 'h' cpu subtype in the MachO header for x86.Jim Grosbach2013-11-161-6/+14
| | | | llvm-svn: 194906
* Implemented aarch64 Neon scalar vmulx_lane intrinsicsAna Pazos2013-11-151-2/+169
| | | | | | | | | | | | | | Implemented aarch64 Neon scalar vfma_lane intrinsics Implemented aarch64 Neon scalar vfms_lane intrinsics Implemented legacy vmul_n_f64, vmul_lane_f64, vmul_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. Implemented legacy vfma_lane_f64, vfms_lane_f64, vfma_laneq_f64, vfms_laneq_f64 intrinsics (v1f64 parameter type) using Neon scalar instructions. llvm-svn: 194888
* Remove unused arguments.Lang Hames2013-11-151-4/+2
| | | | llvm-svn: 194882
* During folding for patchpoint/stackmap instructions, defer creation of new MIsLang Hames2013-11-151-4/+5
| | | | | | | | until we know that folding will be successful. No functional change. llvm-svn: 194880
* [weak vtables] Remove a bunch of weak vtablesJuergen Ributzka2013-11-1558-44/+199
| | | | | | | | | | | This patch removes most of the trivial cases of weak vtables by pinning them to a single object file. Differential Revision: http://llvm-reviews.chandlerc.com/D2068 Reviewed by Andy llvm-svn: 194865
* Make method staticMatt Arsenault2013-11-152-2/+2
| | | | llvm-svn: 194858
* [AArch64] Fix the scalar NEON ACLE functions so that they return float/doubleChad Rosier2013-11-151-4/+4
| | | | | | rather than the vector equivalent. llvm-svn: 194853
* Avoid illegal integer promotion in fastiselBob Wilson2013-11-153-21/+6
| | | | | | | | | | | | | | | | | Stop folding constant adds into GEP when the type size doesn't match. Otherwise, the adds' operands are effectively being promoted, changing the conditions of an overflow. Results are different when: sext(a) + sext(b) != sext(a + b) Problem originally found on x86-64, but also fixed issues with ARM and PPC, which used similar code. <rdar://problem/15292280> Patch by Duncan Exon Smith! llvm-svn: 194840
* R600/SI: Add VReg_96 register class to SIRegisterInfo::hasVGPRs()Tom Stellard2013-11-151-0/+1
| | | | | | This fixes a crash with GNOME settings manager. llvm-svn: 194836
* Add AVX512 unmasked FMA intrinsics and support.Cameron McInally2013-11-151-1/+25
| | | | llvm-svn: 194824
* [mips][msa] lowerMSABitClear() should use SelectionDAG::getNOT() instead of ↵Daniel Sanders2013-11-151-14/+2
| | | | | | | | | using a long-winded equivalent. Now that getConstant(-1, MVT::v2i64) works correctly on MIPS32 we can use SelectionDAG::getNOT() to produce the bitmask. llvm-svn: 194819
* Hopefully fix uninitialized memory read in AArch64AsmParser found by MSan ↵Alexey Samsonov2013-11-151-5/+5
| | | | | | bootstrap bot llvm-svn: 194818
* Fix illegal DAG produced by SelectionDAG::getConstant() for v2i64 typeDaniel Sanders2013-11-151-59/+91
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: When getConstant() is called for an expanded vector type, it is split into multiple scalar constants which are then combined using appropriate build_vector and bitcast operations. In addition to the usual big/little endian differences, the case where the element-order of the vector does not have the same endianness as the elements themselves is also accounted for. For example, for v4i32 on big-endian MIPS, the byte-order of the vector is <3210,7654,BA98,FEDC>. For little-endian, it is <0123,4567,89AB,CDEF>. Handling this case turns out to be a nop since getConstant() returns a splatted vector (so reversing the element order doesn't change the value) This fixes a number of cases in MIPS MSA where calling getConstant() during operation legalization introduces illegal types (e.g. to legalize v2i64 UNDEF into a v2i64 BUILD_VECTOR of illegal i64 zeros). It should also handle bigger differences between illegal and legal types such as legalizing v2i64 into v8i16. lowerMSASplatImm() in the MIPS backend no longer needs to avoid calling getConstant() so this function has been updated in the same patch. For the sake of transparency, the steps I've taken since the review are: * Added 'virtual' to isVectorEltOrderLittleEndian() as requested. This revealed that the MIPS tests were falsely passing because a polymorphic function was not actually polymorphic in the reviewed patch. * Fixed the tests that were now failing. This involved deleting the code to handle the MIPS MSA element-order (which was previously doing an byte-order swap instead of an element-order swap). This left isVectorEltOrderLittleEndian() unused and it was deleted. * Fixed build failures caused by rebasing beyond r194467-r194472. These build failures involved the bset, bneg, and bclr instructions added in these commits using lowerMSASplatImm() in a way that was no longer valid after this patch. Some of these were fixed by calling SelectionDAG::getConstant() instead, others were fixed by a new function getBuildVectorSplat() that provided the removed functionality of lowerMSASplatImm() in a more sensible way. Reviewers: bkramer Reviewed By: bkramer CC: llvm-commits Differential Revision: http://llvm-reviews.chandlerc.com/D1973 llvm-svn: 194811
* [NVPTX] Fix handling of indirect callsJustin Holewinski2013-11-156-12/+46
| | | | | | Using a special machine node is cleaner than an InlineAsm node, and fixes an assertion failure in InstrEmitter llvm-svn: 194810
* Use instr mapping for microMIPS in llvm-mc.Zoran Jovanovic2013-11-152-5/+9
| | | | llvm-svn: 194792
* Add target hook to prevent folding some bitcasted loads.Matt Arsenault2013-11-152-0/+13
| | | | | | | | | | | | | This is to avoid this transformation in some cases: fold (conv (load x)) -> (load (conv*)x) On architectures that don't natively support some vector loads efficiently casting the load to a smaller vector of larger types and loading is more efficient. Patch by Micah Villmow. llvm-svn: 194783
* [llvm-c] Make LLVMGetTargetFromName actually workPeter Zotov2013-11-151-1/+2
| | | | | | LLVMGetTargetFromName used to compare two char* strings directly. llvm-svn: 194771
* [llvm-c] Add missing const qualifiers to LLVMCreateTargetMachinePeter Zotov2013-11-151-3/+4
| | | | llvm-svn: 194770
* [llvm-c] Simplify signature of LLVMGetTargetFromNamePeter Zotov2013-11-151-7/+4
| | | | | | | LLVMGetTargetFromName was not yet present in an LLVM release, so this does not break compatibility. llvm-svn: 194769
* Make all the conditional Mips 16 branches get initially set for theReed Kotler2013-11-153-28/+46
| | | | | | | | | | short form. Constant islands will expand them if they are out of range. Since there is not direct object emitter at this time, it does not have any material affect because the assembler sorts this out. But we need to know for the actual constant island work. We track the difference by putting # 16 inst in the comments. llvm-svn: 194766
* Add addrspacecast instruction.Matt Arsenault2013-11-153-2/+11
| | | | | | Patch by Michele Scandale! llvm-svn: 194760
* R600: Fix scheduling of instructions that use the LDS output queueTom Stellard2013-11-159-51/+116
| | | | | | | | | | | | | | | | | | | | | | | | The LDS output queue is accessed via the OQAP register. The OQAP register cannot be live across clauses, so if value is written to the output queue, it must be retrieved before the end of the clause. With the machine scheduler, we cannot statisfy this constraint, because it lacks proper alias analysis and it will mark some LDS accesses as having a chain dependency on vertex fetches. Since vertex fetches require a new clauses, the dependency may end up spiltting OQAP uses and defs so the end up in different clauses. See the lds-output-queue.ll test for a more detailed explanation. To work around this issue, we now combine the LDS read and the OQAP copy into one instruction and expand it after register allocation. This patch also adds some checks to the EmitClauseMarker pass, so that it doesn't end a clause with a value still in the output queue and removes AR.X and OQAP handling from the scheduler (AR.X uses and defs were already being expanded post-RA, so the scheduler will never see them). Reviewed-by: Vincent Lejeune <vljn at ovi.com> llvm-svn: 194755
* R600/SI: Add processor type for HawaiiTom Stellard2013-11-141-0/+1
| | | | | | | | Patch by: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> llvm-svn: 194752
* R600/SI: Remove redundant legalizeOperands callMatt Arsenault2013-11-141-1/+0
| | | | llvm-svn: 194749
* Add #include raw_ostream.h in lib/Target/R600/SIFixSGPRCopies.cppHans Wennborg2013-11-141-0/+1
| | | | | | This was casuing my release+asserts build on Windows to fail. llvm-svn: 194747
* R600/SI: Specify S_ADDK/S_MULK set SCC and are commutableMatt Arsenault2013-11-141-2/+5
| | | | llvm-svn: 194738
* [AArch64] Remove redundant Neon_immAllOnes/Neon_immAllZeros leaf patterns.Chad Rosier2013-11-141-25/+9
| | | | llvm-svn: 194733
* ARM: produce friendly error for invalid inline asmTim Northover2013-11-141-0/+4
| | | | | | | | | We used to perform an invalid operation on an MVT and crash, which wasn't much fun. Patch by Oliver Stannard. llvm-svn: 194714
* AVX-512: Handled extractelement from mask vector;Elena Demikhovsky2013-11-143-2/+80
| | | | | | Added VMOSHDUP/VMOVSLDUP shuffle instructions. llvm-svn: 194691
* Indentation fixesMatt Arsenault2013-11-142-3/+2
| | | | llvm-svn: 194688
* Add a commentMatt Arsenault2013-11-141-1/+3
| | | | llvm-svn: 194684
* Fix trailing whitespace in debug printingMatt Arsenault2013-11-141-1/+1
| | | | llvm-svn: 194683
* AArch64DAGToDAGISel::SelectVTBL(): Fix a warning. [-Wunused-variable]NAKAMURA Takumi2013-11-141-3/+1
| | | | llvm-svn: 194679
* Minor extension to llvm.experimental.patchpoint: don't require a call.Andrew Trick2013-11-141-11/+16
| | | | | | | | If a null call target is provided, don't emit a dummy call. This allows the runtime to reserve as little nop space as it needs without the requirement of emitting a call. llvm-svn: 194676
* Don't mangle \n and "Rafael Espindola2013-11-141-35/+1
| | | | | | | | | | There is nothing special about quotes and newlines from the object file point of view, only the assembler has to worry about expanding the \n and \". This patch then removes the special handling from the Mangler. llvm-svn: 194667
* R600/SIFixSGPRCopies.cpp: Fix \param to \return. [-Wdocumentation]NAKAMURA Takumi2013-11-141-1/+1
| | | | llvm-svn: 194662
* Whitespace.NAKAMURA Takumi2013-11-141-4/+4
| | | | llvm-svn: 194661
* [AArch64 neon] support poly64 and relevant intrinsic functions.Kevin Qin2013-11-141-0/+9
| | | | llvm-svn: 194659
* Implement aarch64 neon instruction class SIMD misc.Kevin Qin2013-11-143-17/+957
| | | | llvm-svn: 194656
* Implement AArch64 NEON instruction set AdvSIMD (table).Jiangning Liu2013-11-143-0/+168
| | | | llvm-svn: 194648
* R600: Fix uninitialized variable usageTom Stellard2013-11-131-5/+5
| | | | llvm-svn: 194632
* Take care of long short branch immediate instructions for mips16 inReed Kotler2013-11-131-5/+10
| | | | | | constant islands. llvm-svn: 194630
* R600/SI: Add support for private address space load/storeTom Stellard2013-11-1324-134/+402
| | | | | | | Private address space is emulated using the register file with MOVRELS and MOVRELD instructions. llvm-svn: 194626
* R600/SI: Prefer SALU instructions for bit shift operationsTom Stellard2013-11-139-35/+528
| | | | | | | | | | | | | | All shift operations will be selected as SALU instructions and then if necessary lowered to VALU instructions in the SIFixSGPRCopies pass. This allows us to do more operations on the SALU which will improve performance and is also required for implementing private memory using indirect addressing, since the private memory pointers must stay in the scalar registers. This patch includes some fixes from Matt Arsenault. llvm-svn: 194625
* [AArch64] Add support for legacy AArch32 NEON scalar shift by immediateChad Rosier2013-11-131-5/+20
| | | | | | | | instructions. This patch does not include the shift right and accumulate instructions. A number of non-overloaded intrinsics have been remove in favor of their overloaded counterparts. llvm-svn: 194598
* Enable generating legacy IT block for AArch32Weiming Zhao2013-11-135-6/+42
| | | | | | | | | | | | | | By default, the behavior of IT block generation will be determinated dynamically base on the arch (armv8 vs armv7). This patch adds backend options: -arm-restrict-it and -arm-no-restrict-it. The former one restricts the generation of IT blocks (the same behavior as thumbv8) for both arches. The later one allows the generation of legacy IT block (the same behavior as ARMv7 Thumb2) for both arches. Clang will support -mrestrict-it and -mno-restrict-it, which is compatible with GCC. llvm-svn: 194592
* [SystemZ] Add the general form of BCRRichard Sandiford2013-11-132-8/+8
| | | | | | At the moment this is just the MC support. llvm-svn: 194585
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