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* make reciprocal estimate code generation more flexible by adding ↵Sanjay Patel2015-06-047-54/+267
| | | | | | | | | | | | | | | | | | | | | | command-line options (3rd try) The first try (r238051) to land this was reverted due to ExecutionEngine build failure; that was hopefully addressed by r238788. The second try (r238842) to land this was reverted due to BUILD_SHARED_LIBS failure; that was hopefully addressed by r238953. This patch adds a TargetRecip class for processing many recip codegen possibilities. The class is intended to handle both command-line options to llc as well as options passed in from a front-end such as clang with the -mrecip option. The x86 backend is updated to use the new functionality. Only -mcpu=btver2 with -ffast-math should see a functional change from this patch. All other x86 CPUs continue to *not* use reciprocal estimates by default with -ffast-math. Differential Revision: http://reviews.llvm.org/D8982 llvm-svn: 239001
* R600: Re-enable sub-reg livenessTom Stellard2015-06-041-1/+1
| | | | | | The bug in the R600 backend that this uncovered has been fixed. llvm-svn: 238999
* Remove MCELFSymbolFlags.h. It is now internal to MCSymbolELF.Rafael Espindola2015-06-042-3/+1
| | | | llvm-svn: 238996
* Remove getOrCreateSymbolData. There is no MCSymbolData anymore.Rafael Espindola2015-06-033-3/+3
| | | | llvm-svn: 238952
* [Hexagon] Test doesn't work on all platforms. At any rate the uninitialized ↵Colin LeMahieu2015-06-031-4/+0
| | | | | | variable issue was fixed. Removing re-registering ASM backend. llvm-svn: 238949
* [Hexagon] Reapply 238772 OSABI was not correctly set, added empty_elf test ↵Colin LeMahieu2015-06-033-28/+427
| | | | | | to make sure it is. llvm-svn: 238947
* ARM: Thumb2 LDRD/STRD supports independent input/output regsMatthias Braun2015-06-031-20/+22
| | | | | | | | | | | | | | | | The existing code would unnecessarily break LDRD/STRD apart with non-adjacent registers, on thumb2 this is not necessary. Ideally on thumb2 we shouldn't match for ldrd/strd pre-regalloc anymore as there is not reason to set register hints anymore, changing that is something for a future patch however. Differential Revision: http://reviews.llvm.org/D9694 Recommiting after the revert in r238821, the buildbot still failed with the patch removed so there seems to be another reason for the breakage. llvm-svn: 238935
* [arm] Fix r238921. We must handle Constraint_i too.Daniel Sanders2015-06-031-0/+4
| | | | llvm-svn: 238925
* re-apply 238809Asaf Badouh2015-06-035-25/+107
| | | | | | | | | | AVX-512: Implemented GETEXP instruction for KNL and SKX Added rounding mode modifier for SQRTPS/PD Added tests for encoding and intrinsics. CR: http://reviews.llvm.org/D9991 llvm-svn: 238923
* [arm] Distinguish the /U[qytnms]/, 'Uv', 'Q', and 'm' inline assembly memory ↵Daniel Sanders2015-06-032-9/+44
| | | | | | | | | | | | | | | | | | | | | | constraints. Summary: But still handle them the same way since I don't know how they differ on this target. Of these, /U[qytnms]/ do not have backend tests but are accepted by clang. No functional change intended. Reviewers: t.p.northover Reviewed By: t.p.northover Subscribers: t.p.northover, aemerson, llvm-commits Differential Revision: http://reviews.llvm.org/D8203 llvm-svn: 238921
* AVX-512: More code improvements in shuffles, NFCElena Demikhovsky2015-06-031-21/+19
| | | | llvm-svn: 238919
* AVX-512: VSHUFPD instruction selection - code improvementsElena Demikhovsky2015-06-031-34/+36
| | | | llvm-svn: 238918
* AVX-512: Implemented SHUFF32x4/SHUFF64x2/SHUFI32x4/SHUFI64x2 instructions ↵Elena Demikhovsky2015-06-034-9/+61
| | | | | | | | | | for SKX and KNL. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238917
* X86: Added MPX feature and bound registers.Elena Demikhovsky2015-06-035-2/+18
| | | | | | | | | Intel® Memory Protection Extensions (Intel® MPX) is a new feature in Skylake. It is a part of KNL and SKX sets. It is also a part of Skylake client. I added definition of %bnd0 - %bnd3 registers, each register is a pair of 64-bit integers. llvm-svn: 238916
* [X86] Removed (unused) FSRL x86 operationSimon Pilgrim2015-06-034-21/+3
| | | | | | | | | | This patch removes the old X86ISD::FSRL op - which allowed float vectors to use the byte right shift operations (causing a domain switch....). Since the refactoring of the shuffle lowering code this no longer has any use. Differential Revision: http://reviews.llvm.org/D10169 llvm-svn: 238906
* Revert "make reciprocal estimate code generation more flexible by adding ↵Rafael Espindola2015-06-037-267/+54
| | | | | | | | | | command-line options (2nd try)" This reverts commit r238842. It broke -DBUILD_SHARED_LIBS=ON build. llvm-svn: 238900
* Avoid a call to getOrCreateSymbol when we already have the symbol.Rafael Espindola2015-06-031-2/+5
| | | | llvm-svn: 238890
* Pass a MCSymbolELF to a few ELF only functions. NFC.Rafael Espindola2015-06-021-1/+1
| | | | llvm-svn: 238868
* Merge MCELF.h into MCSymbolELF.h.Rafael Espindola2015-06-0213-63/+62
| | | | | | | Now that we have a dedicated type for ELF symbol, these helper functions can become member function of MCSymbolELF. llvm-svn: 238864
* AArch64: fix typo in SMIN far atomics and add testsTim Northover2015-06-021-1/+1
| | | | llvm-svn: 238858
* Push constness through LoopInfo::isLoopHeader and clean it up a bit.Benjamin Kramer2015-06-021-2/+1
| | | | | | NFC. llvm-svn: 238843
* make reciprocal estimate code generation more flexible by adding ↵Sanjay Patel2015-06-027-54/+267
| | | | | | | | | | | | | | | | | | | command-line options (2nd try) The first try (r238051) to land this was reverted due to bot failures that were hopefully addressed by r238788. This patch adds a TargetRecip class for processing many recip codegen possibilities. The class is intended to handle both command-line options to llc as well as options passed in from a front-end such as clang with the -mrecip option. The x86 backend is updated to use the new functionality. Only -mcpu=btver2 with -ffast-math should see a functional change from this patch. All other x86 CPUs continue to *not* use reciprocal estimates by default with -ffast-math. Differential Revision: http://reviews.llvm.org/D8982 llvm-svn: 238842
* AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented ↵Elena Demikhovsky2015-06-021-0/+7
| | | | | | | | | | DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238834
* AVX-512: Shorten implementation of lowerV16X32VectorShuffle()Elena Demikhovsky2015-06-021-39/+61
| | | | | | | using lowerVectorShuffleWithSHUFPS() and other shuffle-helpers routines. Added matching of VALIGN instruction. llvm-svn: 238830
* [mips] Add support for dynamic stack realignment.Vasileios Kalintiris2015-06-028-8/+141
| | | | | | | | | | | | | | | | | | | | Summary: With this change we are able to realign the stack dynamically, whenever it contains objects with alignment requirements that are larger than the alignment specified from the given ABI. We have to use the $fp register as the frame pointer when we perform dynamic stack realignment. In complex stack frames, with variably-sized objects, we reserve additionally the callee-saved register $s7 as the base pointer in order to reference locals. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8633 llvm-svn: 238829
* Revert "ARM: Thumb2 LDRD/STRD supports independent input/output regs"Renato Golin2015-06-021-22/+20
| | | | | | | | | This reverts commit r238795, as it broke the Thumb2 self-hosting buildbot. Since self-hosting issues with Clang are hard to investigate, I'm taking the liberty to revert now, so we can investigate it offline. llvm-svn: 238821
* [AArch64] Add v8.1a atomic instructionsVladimir Sukharev2015-06-028-5/+432
| | | | | | | | | | | | Patch by: Tom Coxon Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8501 llvm-svn: 238818
* [mips] [IAS] Add support for the .set softfloat/hardfloat directives.Toma Tabacu2015-06-023-0/+48
| | | | | | | | | | | | | | Summary: These directives are used to set the current value of the SoftFloat feature. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9074 llvm-svn: 238813
* AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNLElena Demikhovsky2015-06-021-14/+51
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238811
* revert 238809Asaf Badouh2015-06-025-107/+25
| | | | llvm-svn: 238810
* AVX-512: Implemented GETEXP instruction for KNL and SKXAsaf Badouh2015-06-025-25/+107
| | | | | | | Added rounding mode modifier for SQRTPS/PD Added tests for encoding and intrinsics. llvm-svn: 238809
* Create a MCSymbolELF.Rafael Espindola2015-06-022-5/+7
| | | | | | | | | This create a MCSymbolELF class and moves SymbolSize since only ELF needs a size expression. This reduces the size of MCSymbol from 56 to 48 bytes. llvm-svn: 238801
* ARM: Thumb2 LDRD/STRD supports independent input/output regsMatthias Braun2015-06-011-20/+22
| | | | | | | | | | | | | The existing code would unnecessarily break LDRD/STRD apart with non-adjacent registers, on thumb2 this is not necessary. Ideally on thumb2 we shouldn't match for ldrd/strd pre-regalloc anymore as there is not reason to set register hints anymore, changing that is something for a future patch however. Differential Revision: http://reviews.llvm.org/D9694 llvm-svn: 238795
* AArch64: Use CMP;CCMP sequences for and/or/setcc trees.Matthias Braun2015-06-014-72/+255
| | | | | | | | | | | | Previously CCMP/FCCMP instructions were only used by the AArch64ConditionalCompares pass for control flow. This patch uses them for SELECT like instructions as well by matching patterns in ISelLowering. PR20927, rdar://18326194 Differential Revision: http://reviews.llvm.org/D8232 llvm-svn: 238793
* [bpf] fix buildAlexei Starovoitov2015-06-011-2/+2
| | | | | | | | fix breakage due to r238634 Patch by Vijay Subramanian. llvm-svn: 238792
* R600/SI: Don't hardcode pointer typeMatt Arsenault2015-06-011-4/+5
| | | | llvm-svn: 238789
* ARMLoadStoreOptimizer: Fix doxygen comments; NFCMatthias Braun2015-06-011-34/+28
| | | | llvm-svn: 238784
* Revert "[Hexagon] Adding basic ELF relocation generation and testing ↵Rafael Espindola2015-06-013-427/+28
| | | | | | | | | | | | advanced relaxation codepath." This reverts commit r238748. It broke the msan bot: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/4372/steps/check-llvm%20msan/logs/stdio llvm-svn: 238772
* [mips][FastISel] Implement bswap.Vasileios Kalintiris2015-06-011-0/+64
| | | | | | | | | | | | | | | | | | Summary: Implement bswap intrinsic for MIPS FastISel. It's very different for misp32 r1/r2 . Based on a patch by Reed Kotler. Test Plan: bswap1.ll test-suite Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7219 llvm-svn: 238760
* [mips][FastISel] Implement intrinsics memset, memcopy & memmove.Vasileios Kalintiris2015-06-011-7/+89
| | | | | | | | | | | | | | | | | | | | Summary: Implement the intrinsics memset, memcopy and memmove in MIPS FastISel. Make some needed infrastructure fixes so that this can work. Based on a patch by Reed Kotler. Test Plan: memtest1.ll The patch passes test-suite for mips32 r1/r2 and at O0/O2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7158 llvm-svn: 238759
* [mips][FastISel] Implement srem/urem and sdiv/udiv instructions.Vasileios Kalintiris2015-06-011-0/+61
| | | | | | | | | | | | | | | | | | | Summary: Implement the LLVM assembly urem/srem and sdiv/udiv instructions in MIPS FastISel. Based on a patch by Reed Kotler. Test Plan: srem1.ll div1.ll test-suite at O0/O2 for mips32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7028 llvm-svn: 238757
* [mips][FastISel] Implement the select statement for MIPS FastISel.Vasileios Kalintiris2015-06-011-0/+47
| | | | | | | | | | | | | | | | | | Summary: Implement the LLVM IR select statement for MIPS FastISelsel. Based on a patch by Reed Kotler. Test Plan: "Make check" test included now. Passes test-suite at O2/O0 mips32 r1/r2. Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6774 llvm-svn: 238756
* [mips][FastISel] Clobber HI0/LO0 registers in MUL instructions.Vasileios Kalintiris2015-06-011-0/+33
| | | | | | | | | | | | | | | | | | | | | Summary: The contents of the HI/LO registers are unpredictable after the execution of the MUL instruction. In addition to implicitly defining these registers in the MUL instruction definition, we have to mark those registers as dead too. Without this the fast register allocator is running out of registers when the MUL instruction is followed by another one that tries to allocate the AC0 register. Based on a patch by Reed Kotler. Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D9825 llvm-svn: 238755
* Fix relocation selection for foo-. on mips.Rafael Espindola2015-06-011-1/+1
| | | | | | This handles only the 32 bit case. llvm-svn: 238751
* Simplify code, NFC.Rafael Espindola2015-06-011-107/+60
| | | | llvm-svn: 238750
* [Hexagon] Adding basic ELF relocation generation and testing advanced ↵Colin LeMahieu2015-06-013-28/+427
| | | | | | relaxation codepath. llvm-svn: 238748
* AVX-512: Optimized vector shuffle for v16f32 and v16i32 types.Elena Demikhovsky2015-06-011-36/+48
| | | | llvm-svn: 238743
* Re-commit of r238201 with fix for building with shared libraries.Luke Cheeseman2015-06-017-18/+629
| | | | llvm-svn: 238739
* AVX-512: Implemented VRANGEPD and VRANGEPD instructions for SKX.Elena Demikhovsky2015-06-014-6/+34
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238738
* AVX-512: Implemented vector shuffle lowering for v8i64 and v8f64 types.Elena Demikhovsky2015-06-011-33/+102
| | | | | | I removed the vector-shuffle-512-v8.ll, it is auto-generated test, not valid any more. llvm-svn: 238735
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