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* AMDGPU: Fix copies from physical registers in SIFixSGPRCopiesMatt Arsenault2017-04-291-4/+9
| | | | | | | | | This would assert when there were multiple defs of a physical register. We just need to move all of the users of it. llvm-svn: 301730
* Revert r301697 "[IR] Make add/remove Attributes use AttrBuilder instead of ↵Hans Wennborg2017-04-281-4/+5
| | | | | | | | | | | | | | | | | | AttributeList" This broke the Clang build. (Clang-side patch missing?) Original commit message: > [IR] Make add/remove Attributes use AttrBuilder instead of > AttributeList > > This change cleans up call sites and avoids creating temporary > AttributeList objects. > > NFC llvm-svn: 301712
* [RDF] Correctly calculate lane masks for defsKrzysztof Parzyszek2017-04-281-2/+7
| | | | llvm-svn: 301700
* [Hexagon] Do not move a block if it is on a fall-through pathKrzysztof Parzyszek2017-04-281-3/+10
| | | | llvm-svn: 301698
* [IR] Make add/remove Attributes use AttrBuilder instead of AttributeListReid Kleckner2017-04-281-5/+4
| | | | | | | | | This change cleans up call sites and avoids creating temporary AttributeList objects. NFC llvm-svn: 301697
* Make getParamAlignment use argument numbersReid Kleckner2017-04-282-3/+3
| | | | | | | | | | | | | | | | | | The method is called "get *Param* Alignment", and is only used for return values exactly once, so it should take argument indices, not attribute indices. Avoids confusing code like: IsSwiftError = CS->paramHasAttr(ArgIdx, Attribute::SwiftError); Alignment = CS->getParamAlignment(ArgIdx + 1); Add getRetAlignment to handle the one case in Value.cpp that wants the return value alignment. This is a potentially breaking change for out-of-tree backends that do their own call lowering. llvm-svn: 301682
* TargetLowering: Add finalizeLowering() function; NFCMatthias Braun2017-04-282-8/+14
| | | | | | | | | | | | | | | | | Adds a new method finalizeLowering to TargetLoweringBase. This is in preparation for an upcoming commit. This function is meant for target specific adjustments to MachineFrameInfo or register reservations. Move the freezeRegisters() and the hasCopyImplyingStackAdjustment() handling into the new function to prove the concept. As an added bonus GlobalISel no longer missed the hasCopyImplyingStackAdjustment() handling with this. Differential Revision: https://reviews.llvm.org/D32621 llvm-svn: 301679
* AMDGPU: Add new amdgcn.init.exec intrinsicsMarek Olsak2017-04-285-0/+101
| | | | | | | | | | v2: More tests, bug fixes, cosmetic changes. Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, llvm-commits, t-tye Differential Revision: https://reviews.llvm.org/D31762 llvm-svn: 301677
* Kill off the old SimplifyInstruction API by converting remaining users.Daniel Berlin2017-04-281-3/+3
| | | | llvm-svn: 301673
* Use Argument::hasAttribute and AttributeList::ReturnIndex moreReid Kleckner2017-04-285-52/+38
| | | | | | | | | | | This eliminates many extra 'Idx' induction variables in loops over arguments in CodeGen/ and Target/. It also reduces the number of places where we assume that ReturnIndex is 0 and that we should add one to argument numbers to get the corresponding attribute list index. NFC llvm-svn: 301666
* Clean up DIExpression::prependDIExpr a little. (NFC)Adrian Prantl2017-04-281-4/+3
| | | | llvm-svn: 301662
* [bpf] add bigendian support to disassemblerAlexei Starovoitov2017-04-281-7/+19
| | | | | | | | | . swap 4-bit register encoding, 16-bit offset and 32-bit imm to support big endian archs . add a test Reported-by: David S. Miller <davem@davemloft.net> Signed-off-by: Alexei Starovoitov <ast@kernel.org> llvm-svn: 301653
* Move variable local to where ita used. NFCI.Simon Pilgrim2017-04-281-1/+1
| | | | llvm-svn: 301646
* [ARM] GlobalISel: fixup r301632Diana Picus2017-04-281-42/+0
| | | | | | | Actually remove ARMInstructionSelector.h... Forgot to stage the removal in the previous commit. llvm-svn: 301633
* [ARM] GlobalISel: Get rid of ARMInstructionSelector.h. NFC.Diana Picus2017-04-283-3/+31
| | | | | | | | | Declare the ARMInstructionSelector in an anonymous namespace, to make it more in line with the other targets which were migrated to this in r299637 in order to avoid TableGen'erated headers being included in non-GlobalISel builds. llvm-svn: 301632
* [DebugInfo][X86] Improve X86 Optimize LEAs handling of debug values.Andrew Ng2017-04-281-7/+48
| | | | | | | | | | | | | | | This is a follow up to the fix in r298360 to improve the handling of debug values when redundant LEAs are removed. The fix in r298360 effectively discarded the debug values. This patch now attempts to preserve the debug values by using the DWARF DW_OP_stack_value operation via prependDIExpr. Moved functions appendOffset and prependDIExpr from Local.cpp to DebugInfoMetadata.cpp and made them available as static member functions of DIExpression. Differential Revision: https://reviews.llvm.org/D31604 llvm-svn: 301630
* [WebAssembly] Update calls to computeKnownBits after the changes from r301620.Craig Topper2017-04-282-5/+6
| | | | | | I didn't realize WebAssembly wasn't a default build target so I missed that changes were needed. llvm-svn: 301629
* [X86][NFC] Refactor RepMovsRepeats in preparation for D32481.Clement Courbet2017-04-281-49/+45
| | | | | | Differential Revision: https://reviews.llvm.org/D32583 llvm-svn: 301628
* [SelectionDAG] Use KnownBits struct in DAG's computeKnownBits and ↵Craig Topper2017-04-2821-208/+199
| | | | | | | | | | | | simplifyDemandedBits This patch replaces the separate APInts for KnownZero/KnownOne with a single KnownBits struct. This is similar to what was done to ValueTracking's version recently. This is largely a mechanical transformation from KnownZero to Known.Zero. Differential Revision: https://reviews.llvm.org/D32569 llvm-svn: 301620
* [SelectionDAG] Use various APInt methods to reduce temporary APInt creationCraig Topper2017-04-281-1/+1
| | | | | | This patch uses various APInt methods to reduce the number of temporary APInts. These were all found while working through converting SelectionDAG's computeKnownBits to also use the KnownBits struct recently added to the ValueTracking version. llvm-svn: 301618
* [APInt] Use inplace shift methods where possible. NFCICraig Topper2017-04-282-16/+15
| | | | llvm-svn: 301612
* [AMDGPU] DPP: add support for GFX9Sam Kolton2017-04-271-1/+1
| | | | | | | | | | Reviewers: artem.tamazov Subscribers: arsenm, kzhuravl, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D32588 llvm-svn: 301551
* Fix typo and place comment close to its targetKrzysztof Parzyszek2017-04-271-5/+6
| | | | | | | | Patch by Wei-Ren Chen. Differential Revision: https://reviews.llvm.org/D32594 llvm-svn: 301546
* [mips][microMIPS] Adding code size reduction pass for MicroMIPSZoran Jovanovic2017-04-274-0/+338
| | | | | | | | | | | | | | | Author: milena.vujosevic.janicic Reviewers: sdardis The code implements size reduction pass for MicroMIPS. Load and store instructions are examined and transformed, if possible. lw32 instruction is transformed into 16-bit instruction lwsp sw32 instruction is transformed into 16-bit instruction swsp Arithmetic instrcutions are examined and transformed, if possible. addu32 instruction is transformed into 16-bit instruction addu16 subu32 instruction is transformed into 16-bit instruction subu16 Differential Revision: https://reviews.llvm.org/D15144 llvm-svn: 301540
* [SystemZ] Remove incorrect assert in SystemZTTIImplJonas Paulsson2017-04-271-1/+0
| | | | | | | | | In getCmpSelInstrCost(), CondTy may actually be scalar while ValTy is a vector when LoopVectorizer is the caller. Therefore the assert that CondTy must be a vector type if ValTy is was wrong and is now removed. Review: Ulrich Weigand llvm-svn: 301533
* [ARM] GlobalISel: Fix extended stack operandsDiana Picus2017-04-271-3/+12
| | | | | | | | | | | | | | Fix a crash when trying to extend a value passed as a sign- or zero-extended stack parameter. The cause of the crash was that we were setting the size of the loaded value to 32 bits, and then tyring to extend again to 32 bits. This patch addresses the issue by also introducing a G_TRUNC after the load. This will leave the unused bits to their original values set by the caller, while being consistent about the types. For values that are not extended, we just use a smaller load. llvm-svn: 301531
* [GlobalISel][X86] handle not symmetric G_COPYIgor Breger2017-04-271-2/+13
| | | | | | | | | | | | | | Summary: handle not symmetric G_COPY Reviewers: zvi, guyblank Reviewed By: guyblank Subscribers: rovka, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D32420 llvm-svn: 301523
* [CodeGen][NFC] Rename 'Src' to 'Val'.Clement Courbet2017-04-271-7/+7
| | | | | | | | | 'Src' looks like it was borrowed from memcpy, 'Val' makes more sense for memset and is consistent with naming within the function. Differential Revision: https://reviews.llvm.org/D32580 llvm-svn: 301521
* AMDGPU: Fix assert in schedulerKonstantin Zhuravlyov2017-04-271-1/+2
| | | | | | | | Assert is triggered if DBG_VALUE is first instruction in BB Differential Revision: https://reviews.llvm.org/D32572 llvm-svn: 301511
* Lanai: Remove unnecessary canRealignStack() override; NFCMatthias Braun2017-04-262-8/+0
| | | | | | | | It was doing the same as the base implementation and was irritating me when I was searching for backends that have custom behavior for canRealignStack. llvm-svn: 301495
* [AMDGPU][MC] Added arg checks for vmcnt, expcnt, lgkmcnt helpersDmitry Preobrazhensky2017-04-261-16/+48
| | | | | | | | | | | | | | Summary of changes: - corrected vmcnt, expcnt, lgkmcnt helpers to checks their argument for truncation; - added saturated versions of these helpers. See bug 32711 for details: https://bugs.llvm.org//show_bug.cgi?id=32711 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D32546 llvm-svn: 301439
* [ValueTracking] Introduce a KnownBits struct to wrap the two APInts for ↵Craig Topper2017-04-261-4/+4
| | | | | | | | | | | | | | | | computeKnownBits This patch introduces a new KnownBits struct that wraps the two APInt used by computeKnownBits. This allows us to treat them as more of a unit. Initially I've just altered the signatures of computeKnownBits and InstCombine's simplifyDemandedBits to pass a KnownBits reference instead of two separate APInt references. I'll do similar to the SelectionDAG version of computeKnownBits/simplifyDemandedBits as a separate patch. I've added a constructor that allows initializing both APInts to the same bit width with a starting value of 0. This reduces the repeated pattern of initializing both APInts. Once place default constructed the APInts so I added a default constructor for those cases. Going forward I would like to add more methods that will work on the pairs. For example trunc, zext, and sext occur on both APInts together in several places. We should probably add a clear method that can be used to clear both pieces. Maybe a method to check for conflicting information. A method to return (Zero|One) so we don't write it out everywhere. Maybe a method for (Zero|One).isAllOnesValue() to determine if all bits are known. I'm sure there are many other methods we can come up with. Differential Revision: https://reviews.llvm.org/D32376 llvm-svn: 301432
* Reverts commit r301424, r301425 and r301426Sanjoy Das2017-04-262-14/+14
| | | | | | | | | | | | Commits were: "Use WeakVH instead of WeakTrackingVH in AliasSetTracker's UnkownInsts" "Add a new WeakVH value handle; NFC" "Rename WeakVH to WeakTrackingVH; NFC" The changes assumed pointers are 8 byte aligned on all architectures. llvm-svn: 301429
* Rename WeakVH to WeakTrackingVH; NFCSanjoy Das2017-04-262-14/+14
| | | | | | | | | | | | | | | | Summary: I plan to use WeakVH to mean "nulls itself out on deletion, but does not track RAUW" in a subsequent commit. Reviewers: dblaikie, davide Reviewed By: davide Subscribers: arsenm, mehdi_amini, mcrosier, mzolotukhin, jfb, llvm-commits, nhaehnle Differential Revision: https://reviews.llvm.org/D32266 llvm-svn: 301424
* [AMDGPU][MC] Added check for truncation of SOPK imm operandDmitry Preobrazhensky2017-04-263-17/+45
| | | | | | | | | | See bug 30827: https://bugs.llvm.org//show_bug.cgi?id=30827 Reviewers: artem.tamazov, vpykhtin Differential Revision: https://reviews.llvm.org/D32535 llvm-svn: 301418
* [AVR] Remove an unused local variableDylan McKay2017-04-261-1/+0
| | | | llvm-svn: 301413
* [mips] Fix test mips64fpldst.ll with machine verifier enabledSagar Thakur2017-04-261-5/+1
| | | | | | | | | Removed micro mips register classes for gp initialization because gp initialization uses pure mips64 instruction. Even when compiling for micro mips, gp initialization can be done with pure mips64 instructions. Reviewed by Simon Dardis Differential: D32286 llvm-svn: 301394
* [X86] Add missing mayLoad/mayStore attributes to some X86 instructions ↵Ayman Musa2017-04-261-4/+6
| | | | | | | | | | (Continue) Complete the patch committed in rL300190. Differential Revision: https://reviews.llvm.org/D32287 llvm-svn: 301393
* [mips] Rework a portion of MipsCC interface. (NFC)Simon Dardis2017-04-264-21/+27
| | | | | | | | | | | | | | | | | r299766 contained a "conditional move or jump depends on uninitialized value" fault, identified by valgrind. This occurred as MipsFastISel::finishCall(..) used CCState over MipsCCState. The latter is required for the TableGen'd calling convention logic due to reliance on pre-analyzing type information to lower call results/returns of vectors correctly. This change modifies the MipsCC AnalyzeCallResult to be useful with both the SelectionDAG and FastISel lowering logic. Reviewers: slthakur Differential Revision: https://reviews.llvm.org/D32004 llvm-svn: 301392
* PR31007 and PR27884 will be closed: a possibility to compile constants like ↵Andrew V. Tischenko2017-04-261-0/+2
| | | | | | 0bH is now supported in MS asm. llvm-svn: 301390
* [X86][SSE2] Fix asm string for movq (Move Quadword) instruction.Ayman Musa2017-04-261-11/+11
| | | | | | | | Replace "mov{d|q}" with "movq". Differential Revision: https://reviews.llvm.org/D32220 llvm-svn: 301386
* [AMDGPU] Garbage collect dead code. NFCI.Davide Italiano2017-04-261-10/+0
| | | | llvm-svn: 301375
* [MSP430] Fix PR32769: Select8 and Select16 need to have SR in Uses.Vadzim Dambrouski2017-04-261-0/+2
| | | | | | | | | | | If Select pseudo instruction doesn't have use SR, then CMP instructions are being marked as dead and later can be removed by MachineCSE pass. This leads to incorrect code generation. Differential Revision: https://reviews.llvm.org/D32473 llvm-svn: 301372
* [AVR] Do not kill the dest register for a pseudo instructionDylan McKay2017-04-251-1/+1
| | | | | | | It caused the register to later be dead, which would trigger a verifier error. llvm-svn: 301368
* AMDGPU: Shift down reserved SP register like scratch wave offsetMatt Arsenault2017-04-252-17/+59
| | | | llvm-svn: 301367
* AMDGPU: Clean up VOP3NoMods patternMatt Arsenault2017-04-253-35/+22
| | | | | | | There is no need to copy the operands or inspect the sources. Also remove some unnecessary clamp/omod usage. llvm-svn: 301363
* AMDGPU: Fix ValueKind code object metadata for imagesKonstantin Zhuravlyov2017-04-251-12/+12
| | | | | | Differential Revision: https://reviews.llvm.org/D32504 llvm-svn: 301360
* [Hexagon] Only increment debug counters if debug option is presentKrzysztof Parzyszek2017-04-251-6/+11
| | | | llvm-svn: 301346
* [SelectionDAG] Added getBuildVector(ArrayRef<SDUse>) helper.Simon Pilgrim2017-04-251-4/+4
| | | | llvm-svn: 301322
* [AVR] Support the LDWRdPtr instruction with the same Src+Dst registerDylan McKay2017-04-251-52/+75
| | | | llvm-svn: 301313
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