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* [SystemZ] Use DSGFR over DSGR in more casesRichard Sandiford2013-07-024-6/+12
| | | | | | | | | | Fixes some cases where we were using full 64-bit division for (sdiv i32, i32) and (sdiv i64, i32). The "32" in "SDIVREM32" just refers to the second operand. The first operand of all *DIVREM*s is a GR128. llvm-svn: 185435
* [SystemZ] Use MVC to spill loads and storesRichard Sandiford2013-07-023-13/+113
| | | | | | | | | | | | | | | | | | | | | Try to use MVC when spilling the destination of a simple load or the source of a simple store. As explained in the comment, this doesn't yet handle the case where the load or store location is also a frame index, since that could lead to two simultaneous scavenger spills, something the backend can't handle yet. spill-02.py tests that this restriction kicks in, but unfortunately I've not yet found a case that would fail without it. The volatile trick I used for other scavenger tests doesn't work here because we can't use MVC for volatile accesses anyway. I'm planning on relaxing the restriction later, hopefully with a test that does trigger the problem... Tests @f8 and @f9 also showed that L(G)RL and ST(G)RL were wrongly classified as SimpleBDX{Load,Store}. It wouldn't be easy to test for that bug separately, which is why I didn't split out the fix as a separate patch. llvm-svn: 185434
* [SystemZ] Add the MVC instructionRichard Sandiford2013-07-028-124/+243
| | | | | | | | | This is the first use of D(L,B) addressing, which required a fair bit of surgery. For that reason, the patch just adds the instruction definition and the associated assembler and disassembler support. A later patch will actually make use of it for codegen. llvm-svn: 185433
* [XCore] Fix instruction selection for zext, mkmsk instructions.Richard Osborne2013-07-022-2/+2
| | | | | | | | | | | r182680 replaced CountLeadingZeros_32 with a template function countLeadingZeros that relies on using the correct argument type to give the right result. The type passed in the XCore backend after this revision was incorrect in a couple of places. Patch by Robert Lytton. llvm-svn: 185430
* Fix ARM EHABI compact model 1 and 2 without handlerdata.Logan Chien2013-07-021-3/+13
| | | | | | | | | | | | | | According to ARM EHABI section 9.2, if the __aeabi_unwind_cpp_pr1() or __aeabi_unwind_cpp_pr2() is used, then the handler data must be emitted after the unwind opcodes. The handler data consists of several words, and should be terminated by zero. In case that the .handlerdata directive is not specified by the programmer, we should emit zero to terminate the handler data. llvm-svn: 185422
* Cleanup PPC Altivec registers in CSR lists and improve VRSAVE handlingHal Finkel2013-07-024-35/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple of (small) related changes here: 1. The printed name of the VRSAVE register has been changed from VRsave to vrsave in order to match the name accepted by GNU binutils. 2. Support for parsing vrsave has been added to the asm parser (it seems that there was no test case specifically covering this code, so I've added one). 3. The list of Altivec registers, which was common to all calling conventions, has been separated out. This allows us to define the base CSR lists, and then lists for each ABI with Altivec included. This allows SjLj, for example, to work correctly on non-Altivec targets without using unnatural definitions of the NoRegs CSR list. 4. VRSAVE is now always reserved on non-Darwin targets and all Altivec registers are reserved when Altivec is disabled. With these changes, it is now possible to compile a function containing __builtin_unwind_init() on Linux/PPC64 with debugging information. This did not work previously because GNU binutils assumes that all .cfi_offset offsets will be 8-byte aligned on PPC64 (and errors out if you provide a non-8-byte-aligned offset). This is not true for the vrsave register, however, because this register is used only on Darwin, GCC does not bother printing a .cfi_offset entry for it (even though there is a slot in the stack frame for it as specified by the ABI). This change allows us to do the same: we will also not print .cfi_offset directives for vrsave. llvm-svn: 185409
* [mips] Add new InstrItinClasses for move from/to coprocessor instructions andAkira Hatanaka2013-07-024-56/+70
| | | | | | | | floating point loads and stores. No changes in functionality. llvm-svn: 185399
* [PowerPC] Add support for TLS data relocationsUlrich Weigand2013-07-011-0/+9
| | | | | | | | | | This adds support for TLS data relocations and modifiers: .quad target@dtpmod .quad target@tprel .quad target@dtprel Currently exploited by the asm parser only. llvm-svn: 185394
* Change if (cond) ... else llvm_unreachable("text") to assert(cond && "text") ...Richard Trieu2013-07-011-7/+5
| | | | llvm-svn: 185392
* PR16493: DebugInfo with TLS on PPC crashing due to invalid relocationDavid Blaikie2013-07-012-0/+9
| | | | | | | | Restrict the current TLS support to X86 ELF for now. Test that we don't produce it on PPC & we can flesh that test case out with the right thing once someone implements it. llvm-svn: 185389
* [PowerPC] Support all condition register logical instructionsUlrich Weigand2013-07-011-5/+32
| | | | | | | This adds support for all missing condition register logical instructions and extended mnemonics to the asm parser. llvm-svn: 185387
* Add a newline.Chad Rosier2013-07-011-1/+1
| | | | llvm-svn: 185385
* Index: test/CodeGen/PowerPC/reloc-align.llBill Schmidt2013-07-012-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | =================================================================== --- test/CodeGen/PowerPC/reloc-align.ll (revision 0) +++ test/CodeGen/PowerPC/reloc-align.ll (revision 0) @@ -0,0 +1,34 @@ +; RUN: llc -mcpu=pwr7 -O1 < %s | FileCheck %s + +; This test verifies that the peephole optimization of address accesses +; does not produce a load or store with a relocation that can't be +; satisfied for a given instruction encoding. Reduced from a test supplied +; by Hal Finkel. + +target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64" +target triple = "powerpc64-unknown-linux-gnu" + +%struct.S1 = type { [8 x i8] } + +@main.l_1554 = internal global { i8, i8, i8, i8, i8, i8, i8, i8 } { i8 -1, i8 -6, i8 57, i8 62, i8 -48, i8 0, i8 58, i8 80 }, align 1 + +; Function Attrs: nounwind readonly +define signext i32 @main() #0 { +entry: + %call = tail call fastcc signext i32 @func_90(%struct.S1* byval bitcast ({ i8, i8, i8, i8, i8, i8, i8, i8 }* @main.l_1554 to %struct.S1*)) +; CHECK-NOT: ld {{[0-9]+}}, main.l_1554@toc@l + ret i32 %call +} + +; Function Attrs: nounwind readonly +define internal fastcc signext i32 @func_90(%struct.S1* byval nocapture %p_91) #0 { +entry: + %0 = bitcast %struct.S1* %p_91 to i64* + %bf.load = load i64* %0, align 1 + %bf.shl = shl i64 %bf.load, 26 + %bf.ashr = ashr i64 %bf.shl, 54 + %bf.cast = trunc i64 %bf.ashr to i32 + ret i32 %bf.cast +} + +attributes #0 = { nounwind readonly "less-precise-fpmad"="false" "no-frame-pointer-elim"="true" "no-frame-pointer-elim-non-leaf"="true" "no-infs-fp-math"="false" "no-nans-fp-math"="false" "unsafe-fp-math"="false" "use-soft-float"="false" } Index: lib/Target/PowerPC/PPCAsmPrinter.cpp =================================================================== --- lib/Target/PowerPC/PPCAsmPrinter.cpp (revision 185327) +++ lib/Target/PowerPC/PPCAsmPrinter.cpp (working copy) @@ -679,7 +679,26 @@ void PPCAsmPrinter::EmitInstruction(const MachineI OutStreamer.EmitRawText(StringRef("\tmsync")); return; } + break; + case PPC::LD: + case PPC::STD: + case PPC::LWA: { + // Verify alignment is legal, so we don't create relocations + // that can't be supported. + // FIXME: This test is currently disabled for Darwin. The test + // suite shows a handful of test cases that fail this check for + // Darwin. Those need to be investigated before this sanity test + // can be enabled for those subtargets. + if (!Subtarget.isDarwin()) { + unsigned OpNum = (MI->getOpcode() == PPC::STD) ? 2 : 1; + const MachineOperand &MO = MI->getOperand(OpNum); + if (MO.isGlobal() && MO.getGlobal()->getAlignment() < 4) + llvm_unreachable("Global must be word-aligned for LD, STD, LWA!"); + } + // Now process the instruction normally. + break; } + } LowerPPCMachineInstrToMCInst(MI, TmpInst, *this); OutStreamer.EmitInstruction(TmpInst); Index: lib/Target/PowerPC/PPCISelDAGToDAG.cpp =================================================================== --- lib/Target/PowerPC/PPCISelDAGToDAG.cpp (revision 185327) +++ lib/Target/PowerPC/PPCISelDAGToDAG.cpp (working copy) @@ -1530,6 +1530,14 @@ void PPCDAGToDAGISel::PostprocessISelDAG() { if (GlobalAddressSDNode *GA = dyn_cast<GlobalAddressSDNode>(ImmOpnd)) { SDLoc dl(GA); const GlobalValue *GV = GA->getGlobal(); + // We can't perform this optimization for data whose alignment + // is insufficient for the instruction encoding. + if (GV->getAlignment() < 4 && + (StorageOpcode == PPC::LD || StorageOpcode == PPC::STD || + StorageOpcode == PPC::LWA)) { + DEBUG(dbgs() << "Rejected this candidate for alignment.\n\n"); + continue; + } ImmOpnd = CurDAG->getTargetGlobalAddress(GV, dl, MVT::i64, 0, Flags); } else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(ImmOpnd)) { llvm-svn: 185380
* [ARMAsmParser] Sort the ARM register lists based on the encoding value, not theChad Rosier2013-07-011-15/+23
| | | | | | tablegen enum values. This should be the last fix due to fallout from r185094. llvm-svn: 185379
* [mips] Reverse the order of source operands of shift and rotate instructions ↵Akira Hatanaka2013-07-012-8/+8
| | | | | | | | | | that have three register operands. No intended functionality changes. llvm-svn: 185376
* [PowerPC] Also add "msync" aliasUlrich Weigand2013-07-011-0/+1
| | | | | | | This adds an alias for "msync" (which is used on Book E systems instead of "sync"). llvm-svn: 185375
* [mips] Increase the number of floating point control registers available to 32.Akira Hatanaka2013-07-011-4/+9
| | | | | | | Create a dedicated register class for floating point condition code registers and move FCC0 from register class CCR to the new register class. llvm-svn: 185373
* Add jump tables handling for MSP430.Anton Korobeynikov2013-07-012-0/+11
| | | | | | Patch by Job Noorman! llvm-svn: 185364
* Don't form PPC CTR loops for over-sized exit countsHal Finkel2013-07-011-0/+3
| | | | | | | | | | Although you can't generate this from C on PPC64, if you have a loop using a 64-bit counter on PPC32 then you can't form a CTR-based loop for it. This had been cauing the PPCCTRLoops pass to assert. Thanks to Joerg Sonnenberger for providing a test case! llvm-svn: 185361
* AArch64: correct CodeGen of MOVZ/MOVK combinations.Tim Northover2013-07-012-10/+14
| | | | | | | | | | | | According to the AArch64 ELF specification (4.6.8), it's the assembler's responsibility to make sure the shift amount is correct in relocated MOVZ/MOVK instructions. This wasn't being obeyed by either the MCJIT CodeGen or RuntimeDyldELF (which happened to work out well for JIT tests). This commit should make us compliant in this area. llvm-svn: 185360
* Revert r185339 (ARM: relax the atomic release barrier to "dmb ishst")Tim Northover2013-07-011-5/+1
| | | | | | | | | Turns out I'd misread the architecture reference manual and thought that was a load/store-store barrier, when it's not. Thanks for pointing it out Eli! llvm-svn: 185356
* [PowerPC] Fix @got references to local symbolsUlrich Weigand2013-07-011-0/+34
| | | | | | | | | | | A @got reference must always result in a relocation, so that the linker has a chance to set up the GOT entry, even if the symbol happens to be local. Add a PPCELFObjectWriter::ExplicitRelSym routine that enforces a relocation to be emitted for GOT references. llvm-svn: 185353
* [PowerPC] Add "wait" instructionUlrich Weigand2013-07-011-0/+7
| | | | | | This adds the "wait" instruction and its extended mnemonics. llvm-svn: 185350
* [PowerPC] Support "eieio" instructionUlrich Weigand2013-07-012-0/+9
| | | | | | | This adds support for the "eieio" instruction to the asm parser. llvm-svn: 185349
* [PowerPC] Add variants of "sync" instructionUlrich Weigand2013-07-012-5/+12
| | | | | | | This adds support for the "sync $L" instruction with operand, and provides aliases for "lwsync" and "ptesync". llvm-svn: 185344
* ARM: relax the atomic release barrier to "dmb ishst"Tim Northover2013-07-011-1/+5
| | | | | | | | | | | I believe the full "dmb ish" barrier is not required to guarantee release semantics for atomic operations. The weaker "dmb ishst" prevents previous operations being reordered with a store executed afterwards, which is enough. A key point to note (fortunately already correct) is that this barrier alone is *insufficient* for sequential consistency, no matter how liberally placed. llvm-svn: 185339
* [NVPTX] Add support for module-scope inline asmJustin Holewinski2013-07-011-0/+10
| | | | | | | Since we were explicitly not calling AsmPrinter::doInitialization, any module-scope inline asm was not being printed. llvm-svn: 185336
* [NVPTX] We dont use NVBuiltin anymoreJustin Holewinski2013-07-012-3/+0
| | | | llvm-svn: 185335
* [NVPTX] Cut down on physical register defsJustin Holewinski2013-07-013-28/+13
| | | | | | | | We are using virtual registers throughout now, but we still need to keep a few physical registers per class around to keep the infrastructure happy. llvm-svn: 185334
* [NVPTX] 64-bit ADDC/ADDE are not legalJustin Holewinski2013-07-011-0/+3
| | | | llvm-svn: 185333
* [NVPTX] Fix vector loads from parameters that span multiple loads, and fix ↵Justin Holewinski2013-07-012-156/+9
| | | | | | some typos llvm-svn: 185332
* [NVPTX] Handle signext/zeroext attributes properlyJustin Holewinski2013-07-011-19/+25
| | | | | | | | Fix a case where we were incorrectly sign-extending a value when we should have been zero-extending the value. Also change some SIGN_EXTEND to ANY_EXTEND because we really dont care and may have more opportunity to fold subexpressions llvm-svn: 185331
* [NVPTX] Add support for native SIGN_EXTEND_INREG where availableJustin Holewinski2013-07-012-4/+32
| | | | llvm-svn: 185330
* [NVPTX] Add isel patterns for [reg+offset] form of ldg/ldu.Justin Holewinski2013-07-012-112/+430
| | | | llvm-svn: 185329
* [NVPTX] Make sure we zero out high-order 24 bits for 8-bit load into 32-bit ↵Justin Holewinski2013-07-011-1/+2
| | | | | | value llvm-svn: 185328
* R600: Fix an unitialized variable in R600InstrInfo.cppVincent Lejeune2013-06-301-1/+1
| | | | llvm-svn: 185294
* X86: POP*rmm: move address operand to (ins) from (outs).Ahmed Bougacha2013-06-301-3/+3
| | | | llvm-svn: 185292
* NVPTX: Fold otherwise unused variable into assert.Benjamin Kramer2013-06-291-2/+2
| | | | | | Avoids unused variable warnings in release builds. llvm-svn: 185271
* R600: Unbreak GCC build.Benjamin Kramer2013-06-291-1/+2
| | | | | | | operator++ on an enum is not legal. clang happens to accept it anyways, I think that's a known bug. llvm-svn: 185269
* R600: Support schedule and packetization of trans-only instVincent Lejeune2013-06-297-90/+246
| | | | llvm-svn: 185268
* R600: Bank Swizzle now display SCL equivalentVincent Lejeune2013-06-293-12/+12
| | | | llvm-svn: 185267
* Change assert(0 && "text") to llvm_unreachable(0 && "text")Richard Trieu2013-06-281-2/+2
| | | | llvm-svn: 185243
* PPC: Ignore spill/restore requests for VRSAVE (except on Darwin)Hal Finkel2013-06-281-0/+12
| | | | | | | | | | | | This fixes PR16418, which reports that a function calling __builtin_unwind_init() asserts. The cause is that this generates a spill/restore for VRSAVE, and we support that only on Darwin (because VRSAVE is only really used on Darwin). The test case checks only that we don't crash. We can add correctness checks once someone verifies what behavior the function is supposed to have. llvm-svn: 185235
* Fix broken asserts that never fire.Richard Trieu2013-06-281-2/+2
| | | | | | | | Change assert("text") to assert(0 && "text"). The first case is a const char * to bool conversion, which always evaluates to true, never triggering the assert. The second case will always trigger the assert. llvm-svn: 185227
* Remove unused memberDavid Blaikie2013-06-281-4/+0
| | | | llvm-svn: 185219
* R600/SI: Add processor types for each CIK variantTom Stellard2013-06-281-0/+3
| | | | | | | | Patch By: Alex Deucher Reviewed-by: Tom Stellard <thomas.stellard@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> llvm-svn: 185209
* DebugInfo: PR14728: TLS supportDavid Blaikie2013-06-281-0/+6
| | | | | | | | | | | | | | Based on GCC's output for TLS variables (OP_constNu, x@dtpoff, OP_lo_user), this implements debug info support for TLS in ELF. Verified that this output is correct/sufficient on Linux (using gold - if you're using binutils-ld, you'll need something with the fix for http://sourceware.org/bugzilla/show_bug.cgi?id=15685 in it). Support on non-ELF is sort of "arbitrary" at the moment - if Apple folks want to discuss (or just go ahead & implement) how this should work in MachO, etc, I'm open. llvm-svn: 185203
* Fix a PPC rlwimi instruction-selection bugHal Finkel2013-06-281-2/+2
| | | | | | | | | Under certain (evidently rare) circumstances, this code used to convert OR(a, AND(x, y)) into OR(a, x). This was incorrect. While there, I've added a comment to the code immediately above. llvm-svn: 185201
* Fix an off-by-one error. Also make the code a little more explicit in what itChad Rosier2013-06-281-3/+4
| | | | | | is trying to do. llvm-svn: 185191
* Remove unused variables.Eric Christopher2013-06-281-4/+0
| | | | llvm-svn: 185180
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