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* Workaround a couple of Darwin assembler bugs.Evan Cheng2009-08-013-31/+71
| | | | llvm-svn: 77781
* Minor code simplifications.Dan Gohman2009-08-012-8/+1
| | | | llvm-svn: 77768
* Split t2MOVCCs since some assemblers do not recognize mov shifted register ↵Evan Cheng2009-08-012-8/+29
| | | | | | alias with predicate. llvm-svn: 77764
* The X86 maximal stack alignment calculator preserves the CFG. Also,Dan Gohman2009-08-011-2/+9
| | | | | | be more careful about the return value of runOnMachineFunction. llvm-svn: 77758
* X86 floating-point passes don't modify the CFG.Dan Gohman2009-08-012-0/+2
| | | | llvm-svn: 77757
* Fix Thumb2 function call isel. Thumb1 and Thumb2 should share the sameEvan Cheng2009-08-015-72/+40
| | | | | | | | | instructions for calls since BL and BLX are always 32-bit long and BX is always 16-bit long. Also, we should be using BLX to call external function stubs. llvm-svn: 77756
* Use setPreservesAll in X86CodeEmitter.Dan Gohman2009-07-311-0/+1
| | | | llvm-svn: 77755
* llvm-mc: A few more parsing / match tweaks.Daniel Dunbar2009-07-311-11/+42
| | | | | | | | | | | | | | - Operands which are just a label should be parsed as immediates, not memory operands (from the assembler perspective). - Match a few more flavors of immediates. - Distinguish match functions for memory operands which don't take a segment register. - We match the .s for "hello world" now! llvm-svn: 77745
* t2BR_JT is mov pc, it's 2 byte long, not 4.Evan Cheng2009-07-311-9/+9
| | | | llvm-svn: 77744
* Thumb2 movcc need .w suffix.Evan Cheng2009-07-311-3/+3
| | | | llvm-svn: 77743
* PreferredEHDataFormat is always call with data and global, but this wholeChris Lattner2009-07-313-46/+18
| | | | | | | thing is #if0'd out anyway. Just simplify the code by reducing the interface. Not deleting this is essential for Bill's continuing happiness. llvm-svn: 77736
* llvm-mc/X86: Sketch match functions for immediates and memory operands.Daniel Dunbar2009-07-311-37/+112
| | | | | | | Also, change scale value to always be 1 when unspecified to machine MachineInst encoding. llvm-svn: 77728
* move emitUsedDirectiveFor to TargetLoweringObjectFile and rename it toChris Lattner2009-07-312-20/+23
| | | | | | | indicate that it is a predicate, not an emitter. This eliminates TAI dependencies on Mangler and GlobalValue. llvm-svn: 77726
* remove the PPCLinuxTargetAsmInfo implementation of PreferredEHDataFormat,Chris Lattner2009-07-312-35/+0
| | | | | | | | | | because it just calls the default impl. Remove the PPCDarwinTargetAsmInfo version of PreferredEHDataFormat because it just returns DW_EH_PE_absptr unless on 10.6. However, 10.6 doesn't support PPC, so the default impl is just fine. llvm-svn: 77724
* remove a pointless override.Chris Lattner2009-07-312-12/+0
| | | | llvm-svn: 77723
* Move a few more APIs back to 2.5 forms. The only remaining ones left to ↵Owen Anderson2009-07-313-10/+8
| | | | | | | | change back are metadata related, which I'm waiting on to avoid conflicting with Devang. llvm-svn: 77721
* Whitespace and 80-col cleanup.Eric Christopher2009-07-311-153/+167
| | | | llvm-svn: 77718
* switch off of 'Section' onto MCSection. We're not properly usingChris Lattner2009-07-3112-104/+111
| | | | | | MCSection subclasses yet, but this is a step in the right direction. llvm-svn: 77708
* Until we have a "ALIGN" pseudo instruction, have asm printer emitted a .alignEvan Cheng2009-07-311-0/+7
| | | | | | | | to ensure the instruction that follows a TBB (when the number of table entries is odd) is 2-byte aligned. Patch by Sandeep Patel. llvm-svn: 77705
* - Teach TBB / TBH offset limits are 510 and 131070 respectively since the offsetEvan Cheng2009-07-312-9/+14
| | | | | | | is scaled by two. - Teach GetInstSizeInBytes about TBB and TBH. llvm-svn: 77701
* Normalize target registration code.Daniel Dunbar2009-07-311-1/+1
| | | | llvm-svn: 77692
* Reapply r77654 with a fix: MachineFunctionPass's getAnalysisUsageDan Gohman2009-07-312-13/+8
| | | | | | | | shouldn't do AU.setPreservesCFG(), because even though CodeGen passes don't modify the LLVM IR CFG, they may modify the MachineFunction CFG, and passes like MachineLoop are registered with isCFGOnly set to true. llvm-svn: 77691
* refactor section construction in TLOF to be through an explicitChris Lattner2009-07-314-10/+9
| | | | | | initialize method, which can be called when an MCContext is available. llvm-svn: 77687
* fix PR4650: we only track sizes for certain objects, so only put somethingChris Lattner2009-07-311-1/+4
| | | | | | | | into the mergable section if it is one of our special cases. This could obviously be improved, but this is the minimal fix and restores us to the previous behavior. llvm-svn: 77679
* Fix a struct/class mismatch, to silence a MSVC warning.Benjamin Kramer2009-07-311-1/+1
| | | | llvm-svn: 77673
* define target names for std libcalls.Sanjiv Gupta2009-07-312-12/+34
| | | | llvm-svn: 77667
* Revert r77654, it appears to be causing llvm-gcc bootstrap failures, and manyDaniel Dunbar2009-07-312-8/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | failures when building assorted projects with clang. --- Reverse-merging r77654 into '.': U include/llvm/CodeGen/Passes.h U include/llvm/CodeGen/MachineFunctionPass.h U include/llvm/CodeGen/MachineFunction.h U include/llvm/CodeGen/LazyLiveness.h U include/llvm/CodeGen/SelectionDAGISel.h D include/llvm/CodeGen/MachineFunctionAnalysis.h U include/llvm/Function.h U lib/Target/CellSPU/SPUISelDAGToDAG.cpp U lib/Target/PowerPC/PPCISelDAGToDAG.cpp U lib/CodeGen/LLVMTargetMachine.cpp U lib/CodeGen/MachineVerifier.cpp U lib/CodeGen/MachineFunction.cpp U lib/CodeGen/PrologEpilogInserter.cpp U lib/CodeGen/MachineLoopInfo.cpp U lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp D lib/CodeGen/MachineFunctionAnalysis.cpp D lib/CodeGen/MachineFunctionPass.cpp U lib/CodeGen/LiveVariables.cpp llvm-svn: 77661
* llvm-mc: Match a few X86 instructions.Daniel Dunbar2009-07-311-8/+71
| | | | | | | | | | | - This is "experimental" code, I am feeling my way around and working out the best way to do things (and learning tblgen in the process). Comments welcome, but keep in mind this stuff will change radically. - This is enough to match "subb" and friends, but not much else. The next step is to automatically generate the matchers for individual operands. llvm-svn: 77657
* Manage MachineFunctions with an analysis Pass instead of the AnnotableDan Gohman2009-07-312-13/+8
| | | | | | | mechanism. To support this, make MachineFunctionPass a little more complete. llvm-svn: 77654
* When fp is not eliminated, instructions with T2_i12 modes will be changed to ↵Evan Cheng2009-07-302-3/+10
| | | | | | T2_i8 ones. Take that into consideration when determining stack size limit for reserving register scavenging slot. llvm-svn: 77642
* Remove redundant match for frame index from imm8 addrmode, it is handled by ↵David Goodwin2009-07-301-24/+14
| | | | | | the imm12 addrmode. llvm-svn: 77632
* Darwin assembler now recognizes "orn", so remove workaround.David Goodwin2009-07-301-5/+3
| | | | llvm-svn: 77627
* Darwin assembler now supports "rrx", so remove workaround.David Goodwin2009-07-301-2/+1
| | | | llvm-svn: 77625
* Cleanup and include code selection for some frame index cases.David Goodwin2009-07-301-20/+49
| | | | llvm-svn: 77622
* Add missing D* register clobbers for Thumb-2 call.David Goodwin2009-07-301-0/+1
| | | | llvm-svn: 77611
* Minor whitespace tidiness.Dan Gohman2009-07-301-3/+0
| | | | llvm-svn: 77602
* Rename GRAD to GR32_AD, to follow the naming convention of otherDan Gohman2009-07-302-2/+4
| | | | | | classes. And define its SubRegClassList. llvm-svn: 77601
* add a random codegen deficiency.Chris Lattner2009-07-301-0/+46
| | | | llvm-svn: 77598
* Add a note.Evan Cheng2009-07-301-0/+20
| | | | llvm-svn: 77584
* Optimize some common usage patterns of atomic built-ins ↵Evan Cheng2009-07-305-14/+280
| | | | | | | | | | | | __sync_add_and_fetch() and __sync_sub_and_fetch. When the return value is not used (i.e. only care about the value in the memory), x86 does not have to use add to implement these. Instead, it can use add, sub, inc, dec instructions with the "lock" prefix. This is currently implemented using a bit of instruction selection trick. The issue is the target independent pattern produces one output and a chain and we want to map it into one that just output a chain. The current trick is to select it into a merge_values with the first definition being an implicit_def. The proper solution is to add new ISD opcodes for the no-output variant. DAG combiner can then transform the node before it gets to target node selection. Problem #2 is we are adding a whole bunch of x86 atomic instructions when in fact these instructions are identical to the non-lock versions. We need a way to add target specific information to target nodes and have this information carried over to machine instructions. Asm printer (or JIT) can use this information to add the "lock" prefix. llvm-svn: 77582
* Switch obvious clients to Twine instead of utostr (when they were already usingDaniel Dunbar2009-07-301-2/+1
| | | | | | | | | a Twine, e.g., for names). - I am a little ambivalent about this; we don't want the string conversion of utostr, but using overload '+' mixed with string and integer arguments is sketchy. On the other hand, this particular usage is something of an idiom. llvm-svn: 77579
* Keep track of references to mem(cpy,move,set) and then print only one externSanjiv Gupta2009-07-302-2/+41
| | | | | | declaration for them. llvm-svn: 77578
* Add a new register class to describe operands that can't be SP,Dan Gohman2009-07-305-38/+189
| | | | | | | due to x86 encoding restrictions. This is currently off by default because it may cause code quality regressions. This is for PR4572. llvm-svn: 77565
* Eliminate a bunch of redundant tables.Dan Gohman2009-07-301-167/+61
| | | | llvm-svn: 77558
* Lower a 128-bit BUILD_VECTOR with 2 elements to a pair of INSERT_VECTOR_ELTs.Bob Wilson2009-07-301-1/+19
| | | | llvm-svn: 77557
* Use array_endof instead of doing it manually.Dan Gohman2009-07-301-27/+20
| | | | llvm-svn: 77553
* tbb / tbh instructions only branch forward, not backwards.Evan Cheng2009-07-291-2/+4
| | | | llvm-svn: 77522
* Add VFP3 D registers to the DPR register class.Evan Cheng2009-07-291-1/+3
| | | | llvm-svn: 77521
* Move types back to the 2.5 API.Owen Anderson2009-07-294-9/+8
| | | | llvm-svn: 77516
* inline the global 'getInstrOperandRegClass' function into its callersChris Lattner2009-07-291-10/+0
| | | | | | now that TargetOperandInfo does the heavy lifting. llvm-svn: 77508
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