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* convert targets to the new MF.getMachineMemOperand interface.Chris Lattner2010-09-219-30/+42
| | | | llvm-svn: 114391
* fix rdar://8453210, a crash handling a call through a GS relative load.Chris Lattner2010-09-211-1/+7
| | | | | | For now, just disable folding the load into the call. llvm-svn: 114386
* Simplify ARM callee-saved register handling by removing the distinctionJim Grosbach2010-09-203-167/+59
| | | | | | | | | | | | | | | | | | | between the high and low registers for prologue/epilogue code. This was a Darwin-only thing that wasn't providing a realistic benefit anymore. Combining the save areas simplifies the compiler code and results in better ARM/Thumb2 codegen. For example, previously we would generate code like: push {r4, r5, r6, r7, lr} add r7, sp, #12 stmdb sp!, {r8, r10, r11} With this change, we combine the register saves and generate: push {r4, r5, r6, r7, r8, r10, r11, lr} add r7, sp, #12 rdar://8445635 llvm-svn: 114340
* idiom recognition should catch this.Chris Lattner2010-09-191-0/+32
| | | | llvm-svn: 114304
* add a readme.Chris Lattner2010-09-191-0/+25
| | | | llvm-svn: 114303
* X86Subtarget.h: Fix Cygwin's TD.NAKAMURA Takumi2010-09-181-1/+1
| | | | llvm-svn: 114297
* Add the exit instruction to the PTX target.Eric Christopher2010-09-1822-16/+705
| | | | | | Patch by Che-Liang Chiou <clchiou@gmail.com>! llvm-svn: 114294
* Fix build.Michael J. Spencer2010-09-181-0/+1
| | | | llvm-svn: 114292
* Thumb opcodes for thumb calls.Eric Christopher2010-09-181-1/+5
| | | | llvm-svn: 114263
* Add addrmode5 fp load support. Swap float/thumb operand adding to handleEric Christopher2010-09-181-5/+21
| | | | | | thumb with floating point. llvm-svn: 114256
* Floating point stores have a 3rd addressing mode type.Eric Christopher2010-09-181-1/+9
| | | | llvm-svn: 114254
* factor out a simple helper function to create a label for PC-relativeJim Grosbach2010-09-181-19/+17
| | | | | | instructions (PICADD, PICLDR, et.al.) llvm-svn: 114243
* PC-relative pseudo instructions are lowered and printed directly. Any encounterJim Grosbach2010-09-181-3/+2
| | | | | | with one in the generic printing code is an error. llvm-svn: 114242
* Fix vmov.f64 disassembly on targets where sizeof(long) != 8.Benjamin Kramer2010-09-171-2/+2
| | | | llvm-svn: 114240
* Add MC-inst handling for tPICADDJim Grosbach2010-09-171-0/+26
| | | | llvm-svn: 114237
* Add target-specific DAG combiner for BUILD_VECTOR and VMOVRRD. An i64Bob Wilson2010-09-171-0/+27
| | | | | | | | value should be in GPRs when it's going to be used as a scalar, and we use VMOVRRD to make that happen, but if the value is converted back to a vector we need to fold to a simple bit_convert. Radar 8407927. llvm-svn: 114233
* Teach the (non-MC) instruction printer to use the cannonical names for push/pop,Jim Grosbach2010-09-172-4/+72
| | | | | | and shift instructions on ARM. Update the tests to match. llvm-svn: 114230
* Rework arm fast isel branch and compare code.Eric Christopher2010-09-171-8/+70
| | | | llvm-svn: 114226
* Hook up verbose asm comment printing for SOImm operands in MC printerJim Grosbach2010-09-173-8/+6
| | | | llvm-svn: 114215
* trailing whitespaceJim Grosbach2010-09-171-8/+8
| | | | llvm-svn: 114212
* Avoid emitting a PIC base register if no PIC addresses are needed.Dan Gohman2010-09-171-2/+8
| | | | | | This fixes rdar://8396318. llvm-svn: 114201
* Add skeleton infrastructure for the ARMMCCodeEmitter class. Patch by Jason Kim!Jim Grosbach2010-09-173-0/+120
| | | | llvm-svn: 114195
* handle the upper16/lower16 target operand flags on symbol references for MCJim Grosbach2010-09-175-23/+60
| | | | | | instruction lowering. llvm-svn: 114191
* fix rdar://8444631 - encoder crash on 'enter'Chris Lattner2010-09-174-4/+18
| | | | | | What a weird instruction. llvm-svn: 114190
* expand PICLDR MC lowering to handle other PICLDR and PICSTR versions.Jim Grosbach2010-09-171-11/+31
| | | | llvm-svn: 114183
* AlphaSchedule.td: 7bit-ize.NAKAMURA Takumi2010-09-171-1/+1
| | | | llvm-svn: 114173
* fix rdar://8438816 - unrecognized 'fildq' instructionChris Lattner2010-09-161-1/+2
| | | | llvm-svn: 114116
* MC-ization of the PICLDR pseudo. Next up, adding the other variantsJim Grosbach2010-09-162-1/+33
| | | | | | (PICLDRB, et. al.) and PICSTR* llvm-svn: 114098
* Make sure to promote single precision floats to double before extracting themJim Grosbach2010-09-161-2/+4
| | | | | | from the APFloat. llvm-svn: 114096
* Change SPU register re-interpretations from OR to COPY_TO_REGCLASS instruction.Kalle Raiskila2010-09-163-238/+177
| | | | | | | | | | | | | This cleans up after the mess r108567 left in the CellSPU backend. ORCvt-instruction were used to reinterpret registers, and the ORs were then removed by isMoveInstr(). This patch now removes 350 instrucions of format: or $3, $3, $3 (from the 52 testcases in CodeGen/CellSPU). One case of a nonexistant or is checked for. Some moves of the form 'ori $., $., 0' and 'ai $., $., 0' still remain. llvm-svn: 114074
* Remove support for "dregpair" operand modifier, now that it is no longer beingBob Wilson2010-09-162-36/+2
| | | | | | used for anything. llvm-svn: 114067
* When expanding ARM pseudo registers, copy the existing predicate operandsBob Wilson2010-09-161-9/+29
| | | | | | instead of using default predicates on the expanded instructions. llvm-svn: 114066
* store MC FP immediates as a double instead of as an APFloat, thus avoiding anJim Grosbach2010-09-163-4/+8
| | | | | | unnecessary dtor for MCOperand. llvm-svn: 114064
* Add missing break.Bob Wilson2010-09-161-0/+1
| | | | llvm-svn: 114048
* Change VLDMQ and VSTMQ to be pseudo instructions. They are expanded afterBob Wilson2010-09-163-15/+70
| | | | | | | register allocation to VLDMD and VSTMD respectively. This avoids using the dregpair operand modifier. llvm-svn: 114047
* Add support for the 'lane' modifier on vdup operandsJim Grosbach2010-09-151-7/+25
| | | | llvm-svn: 114030
* Remember VLDMQ.Jakob Stoklund Olesen2010-09-151-0/+9
| | | | llvm-svn: 114026
* Add missing break.Jakob Stoklund Olesen2010-09-151-0/+1
| | | | llvm-svn: 114025
* Teach the MC disassembler to handle vmov.f32 and vmov.f64 immediate to registerJim Grosbach2010-09-151-8/+7
| | | | | | | moves. Previously, the immediate was printed as the encoded integer value, which is incorrect. llvm-svn: 114021
* move getRegisterNumbering() to out of ARMBaseRegisterInfo into the helperJim Grosbach2010-09-157-87/+80
| | | | | | | | | functions in ARMBaseInfo.h so it can be used in the MC library as well. For anything bigger than this, we may want a means to have a small support library for shared helper functions like this. Cross that bridge when we come to it. llvm-svn: 114016
* simplify getRegisterNumbering(). Remove the unused isSPVFP argument andJim Grosbach2010-09-152-90/+37
| | | | | | merge the common cases. llvm-svn: 114013
* Refactor uses of getRegisterNumbering() to not need the isSPVFP argument. CheckJim Grosbach2010-09-151-6/+6
| | | | | | if the register is a member of the SPR register class directly instead. llvm-svn: 114012
* Reduce dependencies in the ARM MC instruction printer.Jim Grosbach2010-09-151-1/+1
| | | | llvm-svn: 114009
* Fix spelling typo.Jim Grosbach2010-09-151-1/+1
| | | | llvm-svn: 114008
* Factor out basic enums and hleper functions from ARM.h for cleaner sharingJim Grosbach2010-09-152-101/+129
| | | | | | between the compiler back end and the MC libraries. llvm-svn: 114007
* Add support for floating point immediates to MC instruction printing. ARMJim Grosbach2010-09-152-2/+6
| | | | | | | | | | | VFP instructions use it for loading some constants, so implement that handling. Not thrilled with adding a member to MCOperand, but not sure there's much of a better option that's not pretty fragile (like putting a double in the union instead and just assuming that's good enough). Suggestions welcome... llvm-svn: 113996
* Recognize VST1q64Pseudo and VSTMQ as stack slot stores.Jakob Stoklund Olesen2010-09-151-0/+22
| | | | | | | | | Recognize VLD1q64Pseudo as a stack slot load. Reject these if they are loading or storing a subregister. The API (and VirtRegRewriter) doesn't know how to deal with that. llvm-svn: 113985
* Reapply Gabor's 113839, 113840, and 113876 with a fix for a problemBob Wilson2010-09-151-0/+17
| | | | | | | | encountered while building llvm-gcc for arm. This is probably the same issue that the ppc buildbot hit. llvm::prior works on a MachineBasicBlock::iterator, not a plain MachineInstr. llvm-svn: 113983
* the darwin9-powerpc buildbot keeps consistently crashing,Gabor Greif2010-09-151-16/+0
| | | | | | | | | | backing out following to get it back to green, so I can investigate in peace: svn merge -c -113840 llvm/test/CodeGen/ARM/arm-and-tst-peephole.ll svn merge -c -113876 -c -113839 llvm/lib/Target/ARM/ARMBaseInstrInfo.cpp llvm-svn: 113980
* Move ARM is{LoadFrom,StoreTo}StackSlot closer to their siblings so they won't beJakob Stoklund Olesen2010-09-151-78/+64
| | | | | | | | | | forgotten in the future. Coalesce identical cases in switch. No functional changes intended. llvm-svn: 113979
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