summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
* [mips] Add assembler support for the .cprestore directive.Daniel Sanders2015-09-173-13/+159
| | | | | | | | | | | | | | | | | | Summary: This assembler directive is used in O32 PIC to restore the current function's $gp after executing JAL's. The $gp is first stored on the stack at a user-specified offset. It has the following format: ".cprestore 8" (where 8 is the offset). This fixes llvm.org/PR20967. Patch by Toma Tabacu. Reviewers: seanbruno, tomatabacu Subscribers: brooks, seanbruno, emaste, llvm-commits Differential Revision: http://reviews.llvm.org/D6267 llvm-svn: 247897
* Typos. NFC.Chad Rosier2015-09-171-5/+5
| | | | llvm-svn: 247884
* [mips][microMIPS] Implement TEQ, TGE, TGEU, TLT, TLTU and TNE instructionsZoran Jovanovic2015-09-173-20/+40
| | | | | | Differential Revision: http://reviews.llvm.org/D9658 llvm-svn: 247880
* AVX-512: shufflevector for i1 vectors <2 x i1> .. <64 x i1>Elena Demikhovsky2015-09-172-7/+80
| | | | | | | | | | AVX-512 does not provide an instruction that shuffles mask register. So I do the following way: mask-2-simd , shuffle simd , simd-2-mask Differential Revision: http://reviews.llvm.org/D12727 llvm-svn: 247876
* Try to fix WebAssembly build after r247864Hans Wennborg2015-09-162-2/+2
| | | | llvm-svn: 247870
* Make sure we're negating the assembler predicate - no testcaseEric Christopher2015-09-161-1/+1
| | | | | | | because it isn't being used on anything via the assembler right now. llvm-svn: 247866
* constify the Function parameter to the TTI creation callback andEric Christopher2015-09-1618-21/+24
| | | | | | propagate to all callers/users/etc. llvm-svn: 247864
* [WinEH] Rip out the landingpad-based C++ EH state numbering codeReid Kleckner2015-09-162-40/+0
| | | | | | It never really worked, and the new code is working better every day. llvm-svn: 247860
* [WinEH] Pull Adjectives and CatchObj out of the catchpad arg listReid Kleckner2015-09-161-0/+1
| | | | | | | | | | Clang now passes the adjectives as an argument to catchpad. Getting the CatchObj working is simply a matter of threading another static alloca through codegen, first as an alloca, then as a frame index, and finally as a frame offset. llvm-svn: 247844
* [WinEH] Skip state numbering when no EH pads are presentReid Kleckner2015-09-161-0/+14
| | | | | | | | | Otherwise we'd try to emit the thunk that passes the LSDA to __CxxFrameHandler3. We don't emit the LSDA if there were no landingpads, so we'd end up with an assembler error when trying to write the COFF object. llvm-svn: 247820
* [WebAssembly] Check in an initial CFG Stackifier passDan Gohman2015-09-1612-2/+481
| | | | | | | | | | | | This pass implements a simple algorithm for conversion from CFG to wasm's structured control flow. It doesn't yet handle multiple-entry loops; that will be added in a future patch. It also adds initial support for switch statements. Differential Revision: http://reviews.llvm.org/D12735 llvm-svn: 247818
* propagate fast-math-flags on DAG nodesSanjay Patel2015-09-167-15/+59
| | | | | | | | | | | | | | | | | | | After D10403, we had FMF in the DAG but disabled by default. Nick reported no crashing errors after some stress testing, so I enabled them at r243687. However, Escha soon notified us of a bug not covered by any in-tree regression tests: if we don't propagate the flags, we may fail to CSE DAG nodes because differing FMF causes them to not match. There is one test case in this patch to prove that point. This patch hopes to fix or leave a 'TODO' for all of the in-tree places where we create nodes that are FMF-capable. I did this by putting an assert in SelectionDAG.getNode() to find any FMF-capable node that was being created without FMF ( D11807 ). I then ran all regression tests and test-suite and confirmed that everything passes. This patch exposes remaining work to get DAG FMF to be fully functional: (1) add the flags to non-binary nodes such as FCMP, FMA and FNEG; (2) add the flags to intrinsics; (3) use the flags as conditions for transforms rather than the current global settings. Differential Revision: http://reviews.llvm.org/D12095 llvm-svn: 247815
* [SPARC] Both GNU and Solaris as support eq as condition code for integer ops.Joerg Sonnenberger2015-09-161-0/+1
| | | | llvm-svn: 247804
* [SPARC] Recognize st/stx operations with %fsr argument too.Joerg Sonnenberger2015-09-161-0/+16
| | | | llvm-svn: 247794
* [ARM] Register ARMPreAllocLoadStoreOpt pass with LLVM pass manager.Chad Rosier2015-09-161-2/+14
| | | | llvm-svn: 247791
* [X86] Do not generate 64-bit pops of 32-bit GPRs.Michael Kuperstein2015-09-161-3/+8
| | | | | | | | | | | When trying emit a stack adjustments using pops, frame lowering selects an arbitrary free GPR. It should always select one from an appropriate class... This fixes PR24649. Patch by: amjad.aboud@intel.com Differential Revision: http://reviews.llvm.org/D12609 llvm-svn: 247785
* [X86] Fix emitEpilogue() to make less assumptions about popsMichael Kuperstein2015-09-161-5/+12
| | | | | | | | | | | | | | | This is the mirror image of r242395. When X86FrameLowering::emitEpilogue() looks for where to insert the %esp addition that deallocates stack space used for local allocations, it assumes that any sequence of pop instructions from function exit backwards consists purely of restoring callee-save registers. This may be false, since from some point backward, the pops may be clean-up of stack space allocated for arguments to a call. Patch by: amjad.aboud@intel.com Differential Revision: http://reviews.llvm.org/D12688 llvm-svn: 247784
* [mips][microMIPS] Implement PREFX, LHUE, LBE, LBUE, LHE, LWE, SBE, SHE and ↵Zoran Jovanovic2015-09-164-2/+75
| | | | | | | | SWE instructions Differential Revision: http://reviews.llvm.org/D9189 llvm-svn: 247780
* Revert r247692: Replace Triple with a new TargetTuple in MCTargetDesc/* and ↵Daniel Sanders2015-09-1593-424/+395
| | | | | | | | related. NFC. Eric has replied and has demanded the patch be reverted. llvm-svn: 247702
* [mips][microMIPS] Fix an issue with disassembling lwm32 instructionZoran Jovanovic2015-09-151-1/+1
| | | | | | | Fixed microMIPS disassembler crash on test case generated by llvm-mc-fuzzer. Differential Revision: http://reviews.llvm.org/D12881 llvm-svn: 247698
* [mips] Add support for branch-likely pseudo-instructionsZoran Jovanovic2015-09-154-15/+61
| | | | | | Differential Revision: http://reviews.llvm.org/D10537 llvm-svn: 247697
* [SystemZ] Fix assertion failure in tryBuildVectorShuffleUlrich Weigand2015-09-151-1/+1
| | | | | | | | | | | Under certain circumstances, tryBuildVectorShuffle would attempt to create a BUILD_VECTOR node with an invalid combination of types. This happened when one of the components of the original BUILD_VECTOR was itself a TRUNCATE node. That TRUNCATE was stripped off during intermediate processing to simplify code, but when adding the node back to the result vector, we still need it to get the type right. llvm-svn: 247694
* Re-commit r247683: Replace Triple with a new TargetTuple in MCTargetDesc/* ↵Daniel Sanders2015-09-1593-395/+424
| | | | | | | | | | | | | | | | | | | | | | | | | | | | and related. NFC. Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Thanks go to Pavel Labath for fixing LLDB for me. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247692
* Revert r247684 - Replace Triple with a new TargetTuple ...Daniel Sanders2015-09-1593-424/+395
| | | | | | LLDB needs to be updated in the same commit. llvm-svn: 247686
* Replace Triple with a new TargetTuple in MCTargetDesc/* and related. NFC.Daniel Sanders2015-09-1593-395/+424
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: This is the first patch in the series to migrate Triple's (which are ambiguous) to TargetTuple's (which aren't). For the moment, TargetTuple simply passes all requests to the Triple object it holds. Once it has replaced Triple, it will start to implement the interface in a more suitable way. This change makes some changes to the public C++ API. In particular, InitMCSubtargetInfo(), createMCRelocationInfo(), and createMCSymbolizer() now take TargetTuples instead of Triples. The other public C++ API's have been left as-is for the moment to reduce patch size. This commit also contains a trivial patch to clang to account for the C++ API change. Reviewers: rengolin Subscribers: jyknight, dschuff, arsenm, rampitec, danalbert, srhines, javed.absar, dsanders, echristo, emaste, jholewinski, tberghammer, ted, jfb, llvm-commits, rengolin Differential Revision: http://reviews.llvm.org/D10969 llvm-svn: 247683
* Fix namespace indentation and missing blank lines before 'public:' in ↵Daniel Sanders2015-09-158-91/+103
| | | | | | | | | | *MCAsmInfo.h. NFC. This is to reduce noise in a following commit. Also fixes a couple missing spaces before the reference operator. llvm-svn: 247679
* [mips][microMIPS] Implement CACHEE and PREFE instructions for microMIPS32r6Zoran Jovanovic2015-09-153-1/+31
| | | | | | Differential Revision: http://reviews.llvm.org/D11632 llvm-svn: 247670
* [mips] Added support for various EVA ASE instructions.Daniel Sanders2015-09-159-14/+345
| | | | | | | | | | | | | | | | | | | | Summary: Added support for the following instructions: CACHEE, LBE, LBUE, LHE, LHUE, LWE, LLE, LWLE, LWRE, PREFE, SBE, SHE, SWE, SCE, SWLE, SWRE, TLBINV, TLBINVF This required adding some infrastructure for the EVA ASE. Patch by Scott Egerton. Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D11139 llvm-svn: 247669
* [WebAssembly] Implement int64-to-int32 conversion.Dan Gohman2015-09-151-0/+3
| | | | llvm-svn: 247649
* Improve ISel using across lane min/max reductionJun Bum Lim2015-09-141-53/+190
| | | | | | | | | | | | | | | | | | | | In vectorized integer min/max reduction code, the final "reduce" step is sub-optimal. In AArch64, this change wll combine : %svn0 = vector_shuffle %0, undef<2,3,u,u> %smax0 = smax %0, svn0 %svn3 = vector_shuffle %smax0, undef<1,u,u,u> %sc = setcc %smax0, %svn3, gt %n0 = extract_vector_elt %sc, #0 %n1 = extract_vector_elt %smax0, #0 %n2 = extract_vector_elt $smax0, #1 %result = select %n0, %n1, n2 becomes : %1 = smaxv %0 %result = extract_vector_elt %1, 0 This change extends r246790. llvm-svn: 247575
* [mips] Unified the MipsMemSimm9GPRAsmOperand and MipsMemSimm9AsmOperand ↵Daniel Sanders2015-09-143-24/+10
| | | | | | | | | | | | | | | | | | | operands, NFC. Summary: These operands had the same purpose, however the MipsMemSimm9GPRAsmOperand operand was only for micromips32r6 and the MipsMemSimm9AsmOperand did not have a ParserMatchClass. Patch by Scott Egerton Reviewers: vkalintiris, dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D12730 llvm-svn: 247573
* [ARM] Extract shifts out of multiply-by-constantJohn Brawn2015-09-141-19/+111
| | | | | | | | | | | | | | | Turning (op x (mul y k)) into (op x (lsl (mul y k>>n) n)) is beneficial when we can do the lsl as a shifted operand and the resulting multiply constant is simpler to generate. Do this by doing the transformation when trying to select a shifted operand, as that ensures that it actually turns out better (the alternative would be to do it in PreprocessISelDAG, but we don't know for sure there if extracting the shift would allow a shifted operand to be used). Differential Revision: http://reviews.llvm.org/D12196 llvm-svn: 247569
* [mips] Remove redundant nested-name-specifier. NFCSimon Atanasyan2015-09-141-25/+12
| | | | llvm-svn: 247547
* [mips] Save a copy of MipsABIInfo in the MipsTargetStreamer to escape a ↵Simon Atanasyan2015-09-141-3/+4
| | | | | | | | | | | | | dangling pointer The MipsTargetELFStreamer can receive ABI info from many sources. For example, from the MipsAsmParser instance. Lifetime of the MipsAsmParser can be shorter than MipsTargetELFStreamer's lifetime. In that case we get a dangling pointer to MipsABIInfo. Differential Revision: http://reviews.llvm.org/D12805 llvm-svn: 247546
* [X86][MMX] Added shuffle decodes for MMX/3DNow! shuffles.Simon Pilgrim2015-09-133-2/+77
| | | | | | | Added shuffle decodes for MMX PUNPCK + PSHUFW shuffles. Added shuffle decodes for 3DNow! PSWAPD shuffles. llvm-svn: 247526
* AVX-512: Fixed a bug in OR/XOR operations for 512-bit FP values on KNL.Elena Demikhovsky2015-09-131-2/+16
| | | | | | | | | | | KNL does not have VXORPS, VORPS for 512-bit values. I use integer VPXOR, VPOR that actually do the same. X86ISD::FXOR/FOR are generated as a result of FSUB combining. Differential Revision: http://reviews.llvm.org/D12753 llvm-svn: 247523
* [x86] enable machine combiner reassociations for 128-bit vector logical ↵Sanjay Patel2015-09-121-0/+6
| | | | | | | | | | integer insts (2nd try) The changes in: test/CodeGen/X86/machine-cp.ll are just due to scheduling differences after some logic instructions were reassociated. llvm-svn: 247516
* [X86] Renamed lowerVectorShuffleAsUnpack NFCI.Simon Pilgrim2015-09-121-9/+10
| | | | | | Renamed to lowerVectorShuffleAsPermuteAndUnpack to make it clear that it lowers to more than just a UNPCK instruction. llvm-svn: 247513
* [X86] Moved lowerVectorShuffleWithUNPCK earlier to make reuse easier. NFCI.Simon Pilgrim2015-09-121-63/+59
| | | | llvm-svn: 247511
* revert r247506; need to verify changes in existing testsSanjay Patel2015-09-121-6/+0
| | | | llvm-svn: 247507
* [x86] enable machine combiner reassociations for 128-bit vector logical ↵Sanjay Patel2015-09-121-0/+6
| | | | | | integer insts llvm-svn: 247506
* Fix typos.Bruce Mitchener2015-09-123-8/+8
| | | | | | | | | | Summary: This fixes a variety of typos in docs, code and headers. Subscribers: jholewinski, sanjoy, arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D12626 llvm-svn: 247495
* Use function attribute "stackrealign" to decide whether stackAkira Hatanaka2015-09-111-1/+1
| | | | | | | | | | | | | | | | | realignment should be forced. With this commit, we can now force stack realignment when doing LTO and do so on a per-function basis. Also, add a new cl::opt option "stackrealign" to CommandFlags.h which is used to force stack realignment via llc's command line. Out-of-tree projects currently using -force-align-stack to force stack realignment should make changes to attach the attribute to the functions in the IR. Differential Revision: http://reviews.llvm.org/D11814 llvm-svn: 247450
* [CodeGen] Refactor TLI/AtomicExpand interface to make LLSC explicit.Ahmed Bougacha2015-09-118-23/+36
| | | | | | | | | | | | | | | We used to have this magic "hasLoadLinkedStoreConditional()" callback, which really meant two things: - expand cmpxchg (to ll/sc). - expand atomic loads using ll/sc (rather than cmpxchg). Remove it, and, instead, introduce explicit callbacks: - bool shouldExpandAtomicCmpXchgInIR(inst) - AtomicExpansionKind shouldExpandAtomicLoadInIR(inst) Differential Revision: http://reviews.llvm.org/D12557 llvm-svn: 247429
* [CodeGen] Rename AtomicRMWExpansionKind to AtomicExpansionKind.Ahmed Bougacha2015-09-117-19/+18
| | | | | | This lets us generalize its usage to the other atomic instructions. llvm-svn: 247428
* PPCFrameLowering::emitEpilogue(): Avoid manipulating MBBI on iterator end.NAKAMURA Takumi2015-09-111-1/+1
| | | | | | It caused crash in MachineInstr::hasPropertyInBundle() since r247237. llvm-svn: 247395
* Pass BranchProbability/BlockMass by value instead of const& as they are ↵Cong Hou2015-09-1010-28/+26
| | | | | | small. NFC. llvm-svn: 247357
* [WinEH] Push and pop EBP for 32-bit funcletsReid Kleckner2015-09-101-7/+10
| | | | | | | | The Win32 EH runtime caller does not preserve EBP, even though it does preserve the CSRs (EBX, ESI, EDI) for us. The result was that each finally funclet call would leave the frame pointer off by 12 bytes. llvm-svn: 247348
* AMDGPU: Simplify debug printingMatt Arsenault2015-09-103-13/+8
| | | | llvm-svn: 247345
* AMDGPU: Use StringRef valueMatt Arsenault2015-09-101-1/+1
| | | | llvm-svn: 247344
OpenPOWER on IntegriCloud