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* Fix so "int3" is correctly accepted, added "into" and fixed "int" with anKevin Enderby2010-05-141-2/+4
| | | | | | argument, like "int $4", to not get an Assertion error. llvm-svn: 103791
* Model VLD*_UPD and VLD*odd_UPD pair with REG_SEQUENCE.Evan Cheng2010-05-142-26/+88
| | | | llvm-svn: 103790
* Set isTerminator on TRAP instructions.Dan Gohman2010-05-142-2/+2
| | | | llvm-svn: 103778
* Don't use isBarrier for the PowerPC sync instruction. isBarrier is forDan Gohman2010-05-141-1/+0
| | | | | | control barriers, not memory ordering barriers. llvm-svn: 103777
* Add mayLoad and mayStore flags to instructions which missed them.Dan Gohman2010-05-142-2/+15
| | | | llvm-svn: 103776
* Added a QQQQ register file to model 4-consecutive Q registers.Evan Cheng2010-05-146-52/+189
| | | | llvm-svn: 103760
* Fix comments.Evan Cheng2010-05-141-2/+2
| | | | llvm-svn: 103749
* Add comment about the pseudo registers QQ, each of which is a pair of Q ↵Evan Cheng2010-05-131-0/+5
| | | | | | registers. llvm-svn: 103731
* Fix pr7110: For non-Darwin targets UnspilledCS1GPRs may include high registers.Bob Wilson2010-05-131-1/+3
| | | | | | Do not use those for Thumb1 functions. llvm-svn: 103730
* CMake: fixes 64 bit Visual Studio IDE build. Fixes bug 4936.Oscar Fuentes2010-05-131-1/+6
| | | | | | Patch by Dimitry Andric! llvm-svn: 103727
* Properly set thread-local flag on globals during cpp emissionAnton Korobeynikov2010-05-131-0/+5
| | | | llvm-svn: 103702
* Fix -Asserts warning.Daniel Dunbar2010-05-131-0/+1
| | | | llvm-svn: 103694
* Bring back VLD1q and VST1q and use them for reloading / spilling Q ↵Evan Cheng2010-05-132-29/+83
| | | | | | registers. This allows folding loads and stores into VMOVQ. llvm-svn: 103692
* Expand VMOVQQ into a pair of VMOVQ.Evan Cheng2010-05-131-0/+27
| | | | llvm-svn: 103684
* Mark some pattern-less instructions as neverHasSideEffects.Evan Cheng2010-05-132-1/+9
| | | | llvm-svn: 103683
* reapply r103668 with a fix. Never make "minor syntax changes"Chris Lattner2010-05-132-3/+36
| | | | | | after testing before committing. llvm-svn: 103681
* revert r103668 for now, it is apparently breaking things.Chris Lattner2010-05-122-36/+3
| | | | llvm-svn: 103677
* moffset forms of moves are x86-32 only, make the parserChris Lattner2010-05-122-3/+36
| | | | | | | | lower them to the correct x86-64 instructions since we don't have a clean way to handle this in td files yet. rdar://7947184 llvm-svn: 103668
* Fix some potential issues in the pseudo instruction expansion phase: copy ↵Evan Cheng2010-05-121-35/+61
| | | | | | implicit operands and memoperands. Also, expand instructions even if their defs are "dead" since they may have implicit kill operands. llvm-svn: 103667
* fix the encoding of the obscure "moffset" forms of moves, i386Chris Lattner2010-05-121-5/+6
| | | | | | part first. rdar://7947184 llvm-svn: 103660
* Remove a dead fixme.Evan Cheng2010-05-121-1/+0
| | | | llvm-svn: 103642
* Add support for movi32 of global values to the new (MC) asm printer.Rafael Espindola2010-05-122-5/+25
| | | | llvm-svn: 103576
* vst instructions are modeled as this:Evan Cheng2010-05-121-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | v1024 = REG_SEQUENCE ... v1025 = EXTRACT_SUBREG v1024, 5 v1026 = EXTRACR_SUBREG v1024, 6 = VSTxx <addr>, v1025, v1026 The REG_SEQUENCE ensures the sources that feed into the VST instruction are getting the right register allocation so they form a large super- register. The extract_subreg will be coalesced away all would just work: v1024 = REG_SEQUENCE ... = VSTxx <addr>, v1024:5, v1024:6 The problem is if the coalescer isn't run, the extract_subreg instructions would stick around and there is no assurance v1025 and v1026 will get the right registers. As a short term workaround, teach the NEON pre-allocation pass to transfer the sub-register indices over. An alternative would be do it 2addr pass when reg_sequence's are eliminated. But that *seems* wrong and require updating liveness information. Another alternative is to do this in the scheduler when the instructions are created. But that would mean somehow the scheduler this has to be done for correctness reason. That's yucky as well. So for now, we are leaving this in the target specific pass. llvm-svn: 103540
* MC/X86: Extend suffix matching hack to match 'q' suffix.Daniel Dunbar2010-05-121-1/+3
| | | | llvm-svn: 103535
* MC/Mach-O/x86_64: Add a new hook for checking whether a particular section canDaniel Dunbar2010-05-121-0/+20
| | | | | | | | be diced into atoms, and adjust getAtom() to take this into account. - This fixes relocations to symbols in fixed size literal sections, for example. llvm-svn: 103532
* Add initial kill flag support to FastISel.Dan Gohman2010-05-111-5/+7
| | | | llvm-svn: 103529
* Avoid breaking vstd when reg_sequence is not used.Evan Cheng2010-05-111-1/+2
| | | | llvm-svn: 103513
* Simplify this logic of creating a default Features object.Bill Wendling2010-05-111-26/+8
| | | | llvm-svn: 103507
* I got tired of VISIBILITY_HIDDEN colliding with the gcc enum. Rename itDuncan Sands2010-05-116-6/+6
| | | | | | | to LLVM_LIBRARY_VISIBILITY and introduce LLVM_GLOBAL_VISIBILITY, which is the opposite, for future use by dragonegg. llvm-svn: 103495
* Remove the "WantsWholeFile" concept, as it's no longer needed. CBEDan Gohman2010-05-115-33/+30
| | | | | | | | and the others use the regular addPassesToEmitFile hook now, and llc no longer needs a bunch of redundant code to handle the whole-file case. llvm-svn: 103492
* Implement a bunch more TargetSelectionDAGInfo infrastructure.Dan Gohman2010-05-1156-402/+548
| | | | | | | | Move EmitTargetCodeForMemcpy, EmitTargetCodeForMemset, and EmitTargetCodeForMemmove out of TargetLowering and into SelectionDAGInfo to exercise this. llvm-svn: 103481
* Remove the TargetLowering::getSubtarget() virtual function, whichDan Gohman2010-05-112-2/+2
| | | | | | was unused. TargetMachine::getSubtarget() is used instead. llvm-svn: 103474
* Make SPU backend not assert on jump tables.Kalle Raiskila2010-05-111-0/+3
| | | | llvm-svn: 103466
* Select @llvm.trap to the special B with 1111 condition (i.e. trap) instruction.Evan Cheng2010-05-113-4/+7
| | | | llvm-svn: 103459
* Don't create a StringRef with a NULL value.Bill Wendling2010-05-111-0/+2
| | | | llvm-svn: 103455
* Model some vst3 and vst4 with reg_sequence.Evan Cheng2010-05-112-11/+49
| | | | llvm-svn: 103453
* The getDefaultSubtargetFeatures method of SubtargetFeature did actually return aBill Wendling2010-05-111-8/+20
| | | | | | | | | | | | | | | string of features for that target. However LTO was using that string to pass into the "create target machine" stuff. That stuff needed the feature string to be in a particular form. In particular, it needed the CPU specified first and then the attributes. If there isn't a CPU specified, it required it to be blank -- e.g., ",+altivec". Yuck. Modify the getDefaultSubtargetFeatures method to be a non-static member function. For all attributes for a specific subtarget, it will add them in like normal. It will also take a CPU string so that it can satisfy this horrible syntax. llvm-svn: 103451
* Model some vld3 instructions with REG_SEQUENCE.Evan Cheng2010-05-102-30/+87
| | | | llvm-svn: 103437
* Model vld2 / vst2 with reg_sequence.Evan Cheng2010-05-103-18/+95
| | | | llvm-svn: 103411
* Fix encoding of 'sf' and 'sfh' instructions.Kalle Raiskila2010-05-101-3/+3
| | | | llvm-svn: 103399
* updated handling dllexport in X86AsmPrinterNathan Jeffords2010-05-091-8/+22
| | | | | | changed dllexport code to use EmitBytes instead of EmitRawText, and changed the export option to use /EXPORT: instead of -export: on the windows platform llvm-svn: 103377
* made COFF target dllexport logic apply to all subtargetsNathan Jeffords2010-05-091-28/+26
| | | | llvm-svn: 103373
* break coff symbol definition stuff out into proper MCStreamer callbacks,Chris Lattner2010-05-082-20/+20
| | | | | | patch by Nathan Jeffords! llvm-svn: 103346
* Clean up the conditional for handling of sign_extend_inreg based onJim Grosbach2010-05-071-2/+5
| | | | | | | | whether the extract instructions are available. rdar://7956878 llvm-svn: 103277
* Use overloaded operators instead of DIDescriptor::getNode()Devang Patel2010-05-072-8/+8
| | | | llvm-svn: 103276
* Testing svn access with a note added to documentation.Kalle Raiskila2010-05-071-0/+2
| | | | llvm-svn: 103271
* switch MCSectionCOFF from a syntactic to semantic representation,Chris Lattner2010-05-071-3/+1
| | | | | | patch by Peter Housel! llvm-svn: 103267
* Use VLD2q32 / VST2q32 to reload / spill QQ (pair of Q) registers when stack ↵Evan Cheng2010-05-072-15/+39
| | | | | | slot is sufficiently aligned. Use VLDMD / VSTMD otherwise. llvm-svn: 103235
* Use VSTMD / VLDMD for spills and reloads of Q registers instead of VSTMQ / ↵Evan Cheng2010-05-071-9/+15
| | | | | | VLDQ. The later are aliases which ought to be eliminated but we can't because they are used for storing and loading v2f64 values. llvm-svn: 103234
* When rematerializing, use the debug location of the originalDan Gohman2010-05-071-1/+1
| | | | | | | instruction, rather than a location near where the new instruction is being inserted. llvm-svn: 103232
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