summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* [Hexagon] Fix debug information for local objectsKrzysztof Parzyszek2015-10-194-117/+170
| | | | | | | | | | | | - Isolate the check for the existence of a stack frame into hasFP. - Implement getFrameIndexReference for DWARF address computation. - Use getFrameIndexReference for offset computation in eliminateFrameIndex. - Preserve debug information for dynamically allocated stack objects. - Prefer FP to access local objects at -O0. - Add experimental code to skip allocframe when not strictly necessary (disabled by default). llvm-svn: 250718
* [Hexagon] Delay emission of CFI instructionsKrzysztof Parzyszek2015-10-193-98/+178
| | | | | | | Emit the CFI instructions after all code transformation have been done. This will avoid any interference between CFI instructions and packetization. llvm-svn: 250714
* Remove CRLF newlines. NFC.Benjamin Kramer2015-10-191-6/+6
| | | | llvm-svn: 250698
* Fix mapping of @llvm.arm.ssat/usat intrinsics to ssat/usat instructionsAsiri Rathnayake2015-10-191-4/+4
| | | | | | | | | | | | | The mapping of these two intrinsics in ARMInstrInfo.td had a small omission which lead to their operands not being validated/transformed before being lowered into usat and ssat instructions. This can cause incorrect instructions to be emitted. I've also added tests for the remaining two saturating arithmatic intrinsics @llvm.arm.qadd and @llvm.arm.qsub as they are missing codegen tests. llvm-svn: 250697
* Removed parameter "Consecutive" from isLegalMaskedLoad() / isLegalMaskedStore().Elena Demikhovsky2015-10-192-14/+11
| | | | | | | | | | Originally I planned to use the same interface for masked gather/scatter and set isConsecutive to "false" in this case. Now I'm implementing masked gather/scatter and see that the interface is inconvenient. I want to add interfaces isLegalMaskedGather() / isLegalMaskedScatter() instead of using the "Consecutive" parameter in the existing interfaces. Differential Revision: http://reviews.llvm.org/D13850 llvm-svn: 250686
* [mips][microMIPS] Implement ADDQ.PH, ADDQ_S.W, ADDQH.PH, ADDQH.W, ADDSC, ↵Zlatko Buljan2015-10-193-21/+62
| | | | | | | | ADDU.PH, ADDU_S.QB, ADDWC and ADDUH.QB instructions Differential Revision: http://reviews.llvm.org/D13130 llvm-svn: 250685
* [mips][microMIPS] Implement ABSQ.QB, ABSQ_S.PH, ABSQ_S.W, ABSQ_S.QB, INSV, ↵Zlatko Buljan2015-10-193-10/+76
| | | | | | | | MADD, MADDU, MSUB, MSUBU, MULT and MULTU instructions Differential Revision: http://reviews.llvm.org/D13721 llvm-svn: 250683
* [X86][AVX512DQ] add scalar fpclassAsaf Badouh2015-10-184-6/+61
| | | | | | Differential Revision: http://reviews.llvm.org/D13769 llvm-svn: 250650
* AVX512: Lowering i8/i16 vector CTLZ using the dword LZCNT vector instructionIgor Breger2015-10-182-23/+123
| | | | | | Differential Revision: http://reviews.llvm.org/D13632 llvm-svn: 250649
* [Sparc] Use MCPhysReg instead of unsigned to size static arrays of ↵Craig Topper2015-10-181-6/+7
| | | | | | registers. Should reduce the table size. llvm-svn: 250644
* Make a bunch of static arrays const.Craig Topper2015-10-1812-28/+32
| | | | llvm-svn: 250642
* Use std::find instead of manual loop.Craig Topper2015-10-171-5/+2
| | | | llvm-svn: 250624
* Use std::is_sorted to replace a custom version. Also replace a comparison ↵Craig Topper2015-10-172-16/+4
| | | | | | predicate struct with a lambda. llvm-svn: 250623
* [X86][XOP] Add VPROT instruction opcodesSimon Pilgrim2015-10-175-33/+32
| | | | | | Added X86ISD opcodes for VPROT vector rotate by variable and by immediate. llvm-svn: 250620
* Remove unnecessary 'const' pointed out by David Blaikie.Craig Topper2015-10-171-2/+2
| | | | llvm-svn: 250619
* Replace a custom table sort check with std::is_sorted. Change a function to ↵Craig Topper2015-10-171-17/+8
| | | | | | take ArrayRef instead of pointer and length. NFC llvm-svn: 250615
* Use std::begin/end and std::is_sorted to simplify some code. NFCCraig Topper2015-10-171-8/+5
| | | | llvm-svn: 250614
* [CostModel] Fixed AVX integer shift costsSimon Pilgrim2015-10-171-12/+36
| | | | | | Targets with AVX but without AVX2 were incorrectly reporting costs of 256-bit integer shifts. llvm-svn: 250611
* [X86][FastISel] Teach how to select SSE4A nontemporal stores.Simon Pilgrim2015-10-171-4/+15
| | | | | | | | | | Add FastISel support for SSE4A scalar float / double non-temporal stores Follow up to D13698 Differential Revision: http://reviews.llvm.org/D13773 llvm-svn: 250610
* [Hexagon] Adding skeleton of HVX extension instructions.Colin LeMahieu2015-10-1717-13/+4259
| | | | llvm-svn: 250600
* WebAssembly: don't omit dead vregs from localsJF Bastien2015-10-171-2/+4
| | | | | | | | | | | | | | | | | | Summary: This is a temporary hack until we get around to remapping the vreg numbers to local numbers. Dead vregs cause bad numbering and make consumers sad. We could also just look at debug info an use named locals instead, but vregs have to work properly anyways so there! Reviewers: binji, sunfish Subscribers: jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D13839 llvm-svn: 250594
* WebAssembly: fix the syntax for comparisonsJF Bastien2015-10-171-8/+8
| | | | | | | | | | | | Summary: It has also slightly changed. Reviewers: binji Subscribers: jfb, dschuff, llvm-commits, sunfish Differential Revision: http://reviews.llvm.org/D13837 llvm-svn: 250591
* [WinEH] Fix stack alignment in funclets and ParentFrameOffset calculationReid Kleckner2015-10-162-3/+35
| | | | | | | | | | | | Our previous value of "16 + 8 + MaxCallFrameSize" for ParentFrameOffset is incorrect when CSRs are involved. We were supposed to have a test case to catch this, but it wasn't very rigorous. The main effect here is that calling _CxxThrowException inside a catchpad doesn't immediately crash on MOVAPS when you have an odd number of CSRs. llvm-svn: 250583
* [x86] promote 'add nsw' to a wider type to allow more combinesSanjay Patel2015-10-161-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The motivation for this patch starts with PR20134: https://llvm.org/bugs/show_bug.cgi?id=20134 void foo(int *a, int i) { a[i] = a[i+1] + a[i+2]; } It seems better to produce this (14 bytes): movslq %esi, %rsi movl 0x4(%rdi,%rsi,4), %eax addl 0x8(%rdi,%rsi,4), %eax movl %eax, (%rdi,%rsi,4) Rather than this (22 bytes): leal 0x1(%rsi), %eax cltq leal 0x2(%rsi), %ecx movslq %ecx, %rcx movl (%rdi,%rcx,4), %ecx addl (%rdi,%rax,4), %ecx movslq %esi, %rax movl %ecx, (%rdi,%rax,4) The most basic problem (the first test case in the patch combines constants) should also be fixed in InstCombine, but it gets more complicated after that because we need to consider architecture and micro-architecture. For example, AArch64 may not see any benefit from the more general transform because the ISA solves the sexting in hardware. Some x86 chips may not want to replace 2 ADD insts with 1 LEA, and there's an attribute for that: FeatureSlowLEA. But I suspect that doesn't go far enough or maybe it's not getting used when it should; I'm also not sure if FeatureSlowLEA should also mean "slow complex addressing mode". I see no perf differences on test-suite with this change running on AMD Jaguar, but I see small code size improvements when building clang and the LLVM tools with the patched compiler. A more general solution to the sext(add nsw(x, C)) problem that works for multiple targets is available in CodeGenPrepare, but it may take quite a bit more work to get that to fire on all of the test cases that this patch takes care of. Differential Revision: http://reviews.llvm.org/D13757 llvm-svn: 250560
* Fix assertion failure with fp128 to unsigned i64 conversionAndrew Kaylor2015-10-161-9/+5
| | | | | | | | Patch by Mitch Bodart Differential Revision: http://reviews.llvm.org/D13780 llvm-svn: 250550
* [Hexagon] Split double registersKrzysztof Parzyszek2015-10-163-0/+1217
| | | | llvm-svn: 250549
* [Hexagon] Delete lib/Target/Hexagon/HexagonRemoveSZExtArgs.cppKrzysztof Parzyszek2015-10-163-96/+0
| | | | llvm-svn: 250543
* [Hexagon] Merge adjacent storesKrzysztof Parzyszek2015-10-163-1/+625
| | | | llvm-svn: 250542
* WebAssembly: fix load/store syntaxJF Bastien2015-10-161-51/+51
| | | | | | | | | | | | Summary: The syntax has changed a bit recently. Reviewers: binji Subscribers: llvm-commits, jfb, sunfish, dschuff Differential Revision: http://reviews.llvm.org/D13821 llvm-svn: 250535
* WebAssembly: relooper analysis passJF Bastien2015-10-163-56/+109
| | | | | | | | | | | | Summary: Make the relooper an analysis pass, to convert CFG to AST. Reviewers: sunfish Subscribers: jfb, dschuff Differential Revision: http://reviews.llvm.org/D12744 llvm-svn: 250524
* [AArch64] Implement vector splitting on UADDV.Charlie Turner2015-10-161-0/+32
| | | | | | | | | | | | Summary: Fixes PR25056. Reviewers: mcrosier, junbuml, jmolloy Subscribers: aemerson, rengolin, llvm-commits Differential Revision: http://reviews.llvm.org/D13466 llvm-svn: 250520
* [mips][microMIPS] Implement LB, LBE, LBU and LBUE instructionsHrvoje Varga2015-10-166-1/+140
| | | | | | Differential Revision: http://reviews.llvm.org/D11633 llvm-svn: 250511
* [X86] Add fxsr feature flag for fxsave/fxrestore instructions.Craig Topper2015-10-165-42/+74
| | | | llvm-svn: 250497
* WebAssembly: update syntaxJF Bastien2015-10-161-31/+59
| | | | | | | | | | | | | | | | | | | | | | | | Summary: Follow the same syntax as for the spec repo. Both have evolved slightly independently and need to converge again. This, along with wasmate changes, allows me to do the following: echo "int add(int a, int b) { return a + b; }" > add.c ./out/bin/clang -O2 -S --target=wasm32-unknown-unknown add.c -o add.wack ./experimental/prototype-wasmate/wasmate.py add.wack > add.wast ./sexpr-wasm-prototype/out/sexpr-wasm add.wast -o add.wasm ./sexpr-wasm-prototype/third_party/v8-native-prototype/v8/v8/out/Release/d8 -e "print(WASM.instantiateModule(readbuffer('add.wasm'), {print:print}).add(42, 1337));" As you'd expect, the d8 shell prints out the right value. Reviewers: sunfish Subscribers: jfb, llvm-commits, dschuff Differential Revision: http://reviews.llvm.org/D13712 llvm-svn: 250480
* Revert "[safestack] Fast access to the unsafe stack pointer on AArch64/Android."Evgeniy Stepanov2015-10-154-31/+9
| | | | | | Breaks the hexagon buildbot. llvm-svn: 250461
* [safestack] Fast access to the unsafe stack pointer on AArch64/Android.Evgeniy Stepanov2015-10-154-9/+31
| | | | | | | | | | | | | | | | Android libc provides a fixed TLS slot for the unsafe stack pointer, and this change implements direct access to that slot on AArch64 via __builtin_thread_pointer() + offset. This change also moves more code into TargetLowering and its target-specific subclasses to get rid of target-specific codegen in SafeStackPass. This change does not touch the ARM backend because ARM lowers builting_thread_pointer as aeabi_read_tp, which is not available on Android. llvm-svn: 250456
* x86: preserve flags when folding atomic operationsJF Bastien2015-10-151-15/+20
| | | | | | | | | | D4796 taught LLVM to fold some atomic integer operations into a single instruction. The pattern was unaware that the instructions clobbered flags. I fixed some of this issue in D13680 but had missed INC/DEC. This patch adds the missing EFLAGS definition. llvm-svn: 250438
* x86 FP atomic codegen: don't drop globals, stackJF Bastien2015-10-151-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | Summary: x86 codegen is clever about generating good code for relaxed floating-point operations, but it was being silly when globals and immediates were involved, forgetting where the global was and loading/storing from/to the wrong place. The same applied to hard-coded address immediates. Don't let it forget about the displacement. This fixes https://llvm.org/bugs/show_bug.cgi?id=25171 A very similar bug when doing floating-points atomics to the stack is also fixed by this patch. This fixes https://llvm.org/bugs/show_bug.cgi?id=25144 Reviewers: pete Subscribers: llvm-commits, majnemer, rsmith Differential Revision: http://reviews.llvm.org/D13749 llvm-svn: 250429
* [mips][ias] Implement ulh macro.Daniel Sanders2015-10-152-7/+13
| | | | | | | | | | | | | | Summary: This macro is needed to prevent test/CodeGen/Mips/2008-08-01-AsmInline.ll from failing after the integrated assembler is enabled by default. Reviewers: vkalintiris Subscribers: llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13654 llvm-svn: 250414
* [NVPTX] Remove dead code.Benjamin Kramer2015-10-159-222/+0
| | | | | | I left helpers that look useful for debugging alone. NFC. llvm-svn: 250410
* [mips][mips16] MIPS16 is not a CPU/Architecture but is an ASE.Daniel Sanders2015-10-152-2/+0
| | | | | | | | | | | | | | | | Summary: The -mcpu=mips16 option caused the Integrated Assembler to crash because it couldn't figure out the architecture revision number to write to the .MIPS.abiflags section. This CPU definition has been removed because, like microMIPS, MIPS16 is an ASE to a base architecture. Reviewers: vkalintiris Subscribers: rkotler, llvm-commits, dsanders Differential Revision: http://reviews.llvm.org/D13656 llvm-svn: 250407
* [X86] Rip out orphaned method declarations and other dead code. NFC.Benjamin Kramer2015-10-157-53/+0
| | | | llvm-svn: 250406
* AVX512: Implemented DAG lowering for shuff62x2/shufi62x2 instructions ( ↵Igor Breger2015-10-154-1/+133
| | | | | | | | shuffle packed values at 128-bit granularity ) Differential Revision: http://reviews.llvm.org/D13648 llvm-svn: 250400
* AVX512: Implemented encoding and intrinsics for vpternlogd/q.Igor Breger2015-10-155-4/+98
| | | | | | Differential Revision: http://reviews.llvm.org/D13768 llvm-svn: 250396
* AVX-512: Fixed a bug in shuffle lowering 32-bit modeElena Demikhovsky2015-10-151-6/+35
| | | | | | | | | AVX-512 bit shuffle fails on 32 bit since we create a vector of 64-bit constants. I split 8x64-bit const vector to 16x32 on 32-bit mode. Differential Revision: http://reviews.llvm.org/D13644 llvm-svn: 250390
* Don't pretend AMDGPU backend knows how to custom-lower UDIVREM for vector ↵Artyom Skrobov2015-10-151-1/+1
| | | | | | | | | | | | types; it can't Reviewers: arsenm, jvesely, tstellarAMD Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D13734 llvm-svn: 250384
* [mips][microMIPS] Implement DPA.W.PH, DPAQ_S.W.PH, DPAQ_SA.L.W, ↵Zlatko Buljan2015-10-154-12/+51
| | | | | | | | DPAQX_S.W.PH, DPAQX_SA.W.PH, DPAU.H.QBL, DPAU.H.QBR and DPAX.W.PH instructions Differential Revision: http://reviews.llvm.org/D13376 llvm-svn: 250382
* [mips][microMIPS] Implement BREAK16, LI16, MOVE16, SDBBP16, SUBU16 and XOR16 ↵Hrvoje Varga2015-10-153-13/+68
| | | | | | | | instructions Differential Revision: http://reviews.llvm.org/D11292#inline-103143 llvm-svn: 250381
* [mips][microMIPS] Implement LLE and SCE instructionsHrvoje Varga2015-10-153-0/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D11630 llvm-svn: 250379
* [mips][microMIPS] Implement LWLE, LWRE, SWLE and SWRE instructionsHrvoje Varga2015-10-152-0/+26
| | | | | | Differential Revision: http://reviews.llvm.org/D11631 llvm-svn: 250377
OpenPOWER on IntegriCloud