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* Be gentle to MSVC. C++ is hard, after all.Jakob Stoklund Olesen2010-03-301-2/+3
| | | | llvm-svn: 99855
* Basic implementation of SSEDomainFix pass.Jakob Stoklund Olesen2010-03-293-57/+399
| | | | | | Cross-block inference is primitive and wrong, but the pass is working otherwise. llvm-svn: 99848
* Make isInt?? and isUint?? template specializations of the generic versions. ThisBenjamin Kramer2010-03-299-40/+42
| | | | | | | makes calls a little bit more consistent and allows easy removal of the specializations in the future. Convert all callers to the templated functions. llvm-svn: 99838
* We'll never match these as instructions, just as intrinsics so removeEric Christopher2010-03-291-16/+10
| | | | | | the SDNodes. llvm-svn: 99835
* Remove a bunch of integer width predicate functions in favor of MathExtras.Benjamin Kramer2010-03-294-139/+11
| | | | | | | Most of these were unused, some of them were wrong and unused (isS16Constant<short>, isS10Constant<short>). llvm-svn: 99827
* From Kalle Raiskila:Chris Lattner2010-03-294-14/+158
| | | | | | | | "the bigstack patch for SPU, with testcase. It is essentially the patch committed as 97091, and reverted as 97099, but with the following additions: -in vararg handling, registers are marked to be live, to not confuse the register scavenger -function prologue and epilogue are not emitted, if the stack size is 16. 16 means it is empty - there is only the register scavenger emergency spill slot, which is not used as there is no stack." llvm-svn: 99819
* add a note.Chris Lattner2010-03-291-0/+3
| | | | llvm-svn: 99815
* Add NVTBLFrm to represent A8.6.406 VTBL, VTBX Vector Table Lookup Instructions.Johnny Chen2010-03-292-8/+9
| | | | | | | | | | | | | These instructions use byte index in a control vector (M:Vm) to lookup byte values in a table and generate a new vector (D:Vd). The table is specified via a list of vectors, which can be: {Dn} {Dn D<n+1>} {Dn D<n+1> D<n+2>} {Dn D<n+1> D<n+2> D<n+3>} llvm-svn: 99789
* zap an extra line that Eli noticed!Chris Lattner2010-03-281-1/+0
| | | | llvm-svn: 99770
* fix a type contradition: XCoreISD::RETSP has one argument, not zero.Chris Lattner2010-03-281-1/+1
| | | | llvm-svn: 99760
* remove a pattern with no testcase that doesn't appear to be Chris Lattner2010-03-281-2/+0
| | | | | | matchable: it seems like it would always constant fold. llvm-svn: 99758
* fix integer negates to use the proper type for the zero vectors,Chris Lattner2010-03-281-11/+14
| | | | | | | this also depends on the new "bitconvert dropping" behavior just added to tblgen. llvm-svn: 99757
* fix a typo, bitconvert from node to itself isn't valid.Chris Lattner2010-03-281-1/+1
| | | | llvm-svn: 99755
* fix vnot matching to explicitly specify the type of theChris Lattner2010-03-281-10/+16
| | | | | | | | | input to be v8i8 or v16i8, which buildvectors get canonicalized to. This allows the patterns that were previously using a bare 'vnot' to match, before they couldn't. llvm-svn: 99754
* fix up vnot matching, eliminating a dead pattern, correcting a couple ofChris Lattner2010-03-281-6/+11
| | | | | | | patterns that would never match because of bitcast, and eliminating use of vnot_conv. llvm-svn: 99753
* stop using vnot_convChris Lattner2010-03-281-3/+8
| | | | llvm-svn: 99750
* revert r99743, this is saying that the repmovs instructinos have anChris Lattner2010-03-281-2/+4
| | | | | | *input* of other type, which is the VT. llvm-svn: 99749
* remove a bunch of dead patterns.Chris Lattner2010-03-281-13/+0
| | | | llvm-svn: 99748
* claiming to return other is pointless.Chris Lattner2010-03-281-4/+2
| | | | llvm-svn: 99743
* Improve systemz to model cmp and ucmp nodes as returningChris Lattner2010-03-282-43/+33
| | | | | | their flags correctly. llvm-svn: 99738
* the FPCmp node returns an i32.Chris Lattner2010-03-281-6/+8
| | | | llvm-svn: 99737
* fix some modelling problems exposed by a patch I'm working on. bsr/bsf/ptestChris Lattner2010-03-283-26/+21
| | | | | | nodes all have an EFLAGS result when made by isel lowering. llvm-svn: 99736
* Fix indentation.Bob Wilson2010-03-271-34/+34
| | | | llvm-svn: 99705
* Add a format argument to the N3V and N3VX classes, removing the N3Vf class.Bob Wilson2010-03-272-198/+198
| | | | llvm-svn: 99704
* eliminate the last of the parallel's!Chris Lattner2010-03-272-173/+102
| | | | llvm-svn: 99700
* Add NVMulSLFrm to represent "3-register multiply with scalar" operations and setJohnny Chen2010-03-272-122/+130
| | | | | | | | | | | | it as the format for the appropriate N3V*SL*<> classes. These instructions require special handling of the M:Vm field which encodes the restricted Dm and the lane index within Dm. Examples are A8.6.325 VMLA, VMLAL, VMLS, VMLSL (by scalar): vmlal.s32 q3, d2, d10[0] llvm-svn: 99690
* eliminate almost all the rest of the x86-32 parallels.Chris Lattner2010-03-271-157/+116
| | | | llvm-svn: 99686
* Thumb2 storeFrom/LoadToStackSlot() need to handle tGPR regs directly, not passJim Grosbach2010-03-271-2/+2
| | | | | | | through to the generic version. The generic functions use STR/LDR, but T2 needs the t2STR/t2LDR instead so we get the addressing mode correct. llvm-svn: 99678
* Remove the duplicate multiclass N3VSh_QHSD and use N3VInt_QHSD which is modifiedJohnny Chen2010-03-261-193/+154
| | | | | | | to now take a format argument. N3VDInt<> and N3VQInt<> are modified to take a format argument as well. llvm-svn: 99676
* Add NVExtFrm to represent NEON Vector Extract Instructions, that uses Inst{11-8}Johnny Chen2010-03-262-10/+11
| | | | | | | | | to encode the byte location of the extracted result in the concatenation of the operands, from the least significant end. Modify VEXTd and VEXTq classes to use the format. llvm-svn: 99659
* Add N3RegVShFrm to represent 3-Register Vector Shift Instructions, which do notJohnny Chen2010-03-262-23/+85
| | | | | | | | | | | | | | follow the N3RegFrm's operand order of D:Vd N:Vn M:Vm. The operand order of N3RegVShFrm is D:Vd M:Vm N:Vn (notice that M:Vm is the first src operand). Add a parent class N3Vf which requires passing a Format argument and which the N3V class is modified to inherit from. N3V class represents the "normal" 3-Register NEON Instructions with N3RegFrm. Also add a multiclass N3VSh_QHSD to represent clusters of NEON 3-Register Shift Instructions and replace 8 invocations with it. llvm-svn: 99655
* vldm/vstm can only do up to 16 double-word registers at a time.Jim Grosbach2010-03-261-1/+5
| | | | | | Radar 7797856 llvm-svn: 99630
* Add N3RegFrm to represent "NEON 3 vector register format" instructions.Johnny Chen2010-03-261-2/+3
| | | | | | | Examples are VABA (Vector Absolute Difference and Accumulate), VABAL (Vector Absolute Difference and Accumulate Long), and VABD (Vector Absolute Difference). llvm-svn: 99628
* Do not sibcall if stack needs to be dynamically aligned.Evan Cheng2010-03-261-0/+6
| | | | llvm-svn: 99620
* Allow trivial sibcall of vararg callee when no arguments are being passed.Evan Cheng2010-03-261-2/+3
| | | | llvm-svn: 99598
* Add N2RegVShLFrm and N2RegVShRFrm formats so that the disassembler can easilyJohnny Chen2010-03-262-42/+54
| | | | | | | | | | | dispatch to the appropriate routines to handle the different interpretations of the shift amount encoded in the imm6 field. The Vd, Vm fields are interpreted the same between the two, though. See, for example, A8.6.367 VQSHL, VQSHLU (immediate) for N2RegVShLFrm format and A8.6.368 VQSHRN, VQSHRUN for N2RegVShRFrm format. llvm-svn: 99590
* switch the flag for using NEON for SP floating point to a subtarget 'feature'.Jim Grosbach2010-03-252-16/+11
| | | | | | Re-commit. This time complete with testsuite updates. llvm-svn: 99570
* need to fix 'make check' tests first. revert for a moment.Jim Grosbach2010-03-252-11/+16
| | | | llvm-svn: 99569
* switch the flag for using NEON for SP floating point to a subtarget 'feature'Jim Grosbach2010-03-252-16/+11
| | | | llvm-svn: 99568
* Removed instruction class NI from ARMInstrFormats.td.Johnny Chen2010-03-251-6/+0
| | | | | | It doesn't seem to be used anywhere. llvm-svn: 99566
* switch the use-vml[as] instructions flag to a subtarget 'feature'Jim Grosbach2010-03-253-16/+15
| | | | llvm-svn: 99565
* Add NVDupLnFrm and change NVDupLane class to use that format.Johnny Chen2010-03-251-1/+2
| | | | llvm-svn: 99557
* ARM cortex-a8 doesn't do vmla/vmls well. disable them by default for that cpuJim Grosbach2010-03-251-0/+6
| | | | llvm-svn: 99549
* Add NVCVTFrm (NEON Convert with fractional bits immediate) and modify N2VImm toJohnny Chen2010-03-252-19/+20
| | | | | | expect a Format arg. N2VCvtD/N2VCvtQ are modified to use the NVCVTFrm format. llvm-svn: 99548
* Fix -Asserts warning, again.Daniel Dunbar2010-03-251-0/+1
| | | | llvm-svn: 99542
* Tag SSE2 integer instructions as SSEPackedInt.Jakob Stoklund Olesen2010-03-251-2/+11
| | | | llvm-svn: 99540
* Teach TableGen to understand X.Y notation in the TSFlagsFields strings.Jakob Stoklund Olesen2010-03-253-10/+7
| | | | | | | Remove much horribleness from X86InstrFormats as a result. Similar simplifications are probably possible for other targets. llvm-svn: 99539
* Add a late SSEDomainFix pass that twiddles SSE instructions to avoid domain ↵Jakob Stoklund Olesen2010-03-259-21/+223
| | | | | | | | | | | | | | | | | | | | | | crossings. On Nehalem and newer CPUs there is a 2 cycle latency penalty on using a register in a different domain than where it was defined. Some instructions have equvivalents for different domains, like por/orps/orpd. The SSEDomainFix pass tries to minimize the number of domain crossings by changing between equvivalent opcodes where possible. This is a work in progress, in particular the pass doesn't do anything yet. SSE instructions are tagged with their execution domain in TableGen using the last two bits of TSFlags. Note that not all instructions are tagged correctly. Life just isn't that simple. The SSE execution domain issue is very similar to the ARM NEON/VFP pipeline issue handled by NEONMoveFixPass. This pass may become target independent to handle both. llvm-svn: 99524
* Added a new instruction class NVDupLane to be inherited by VDUPLND and VDUPLNQ,Johnny Chen2010-03-252-20/+31
| | | | | | | instead of the current N2V. Format of NVDupLane instances are set to NEONFrm currently. llvm-svn: 99518
* Reapply Kevin's change 94440, now that Chris has fixed the limitation onBob Wilson2010-03-252-0/+48
| | | | | | opcode values fitting in one byte (svn r99494). llvm-svn: 99514
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