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* [X86] Remove an unneeded ZERO_EXTEND creation from LowerINTRINSIC_W_CHAIN. NFCCraig Topper2019-05-211-2/+1
| | | | | | We were trying to ZERO_EXTEND from an i8 X86ISD::SETCC to i8 again. llvm-svn: 361288
* [X86][SSE] computeKnownBitsForTargetNode - add X86ISD::ANDNP supportSimon Pilgrim2019-05-211-0/+9
| | | | | | Fixes PACKSS-PSHUFB shuffle regressions mentioned on D61692 llvm-svn: 361270
* [PPC64] Update LocalEntry from assigned symbolsFangrui Song2019-05-211-6/+24
| | | | | | | | | | | | | | | | | On PowerPC64 ELFv2 ABI, functions may have 2 entry points: global and local. The local entry point location of a function is stored in the st_other field of the symbol, as an offset relative to the global entry point. In order to make symbol assignments (e.g. .equ/.set) work properly with this, PPCTargetELFStreamer already copies the local entry bits from the source symbol to the destination one, on emitAssignment(). The problem is that this copy is performed only at the assignment location, where the source symbol may not yet have processed the .localentry directive, that sets the local entry. This may cause the destination symbol to end up with wrong local entry information. Other symbol info is not affected by this because, in this case, the destination symbol value is actually a symbol reference. This change keeps track of these assignments, and update all needed st_other fields when finish() is called. Patch by Leandro Lupori! Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D56586 llvm-svn: 361237
* [AArch64] Skip mask checks for masks with an odd number of elements.Florian Hahn2019-05-211-0/+6
| | | | | | | | | | | | | | | | | Some checks in isShuffleMaskLegal expect an even number of elements, e.g. isTRN_v_undef_Mask or isUZP_v_undef_Mask, otherwise they access invalid elements and crash. This patch adds checks to the impacted functions. Fixes PR41951 Reviewers: t.p.northover, dmgreen, samparker Reviewed By: dmgreen Differential Revision: https://reviews.llvm.org/D60690 llvm-svn: 361235
* [AArch64][SVE2] Asm: add integer unary instructions (predicated)Cullen Rhodes2019-05-212-0/+42
| | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: * URECPE, URSQRTE, SQABS, SQNEG The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62129 llvm-svn: 361230
* [AArch64][SVE2] Asm: add integer pairwise arithmetic instructionsCullen Rhodes2019-05-211-0/+7
| | | | | | | | | | | | | | | | Summary: Patch adds support for the following instructions: ADDP, SMAXP, UMAXP, SMINP, UMINP The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62128 llvm-svn: 361229
* [ARM][CGP] Skip nuw in PrepareConstantsSam Parker2019-05-211-72/+52
| | | | | | | | | | | | | | | PrepareConstants step converts add/sub with 'negative' immediates to sub/add with a 'positive' imm to make promotion more simple. nuw already states that the add shouldn't cause an unsigned wrap, so it shouldn't need any tweaking. Plus, we also don't allow a sub with a 'negative' immediate to be safe wrap, so this functionality has been removed. The PrepareConstants step now just handles the add instructions that we've determined would be safe if they wrap around zero. Differential Revision: https://reviews.llvm.org/D62057 llvm-svn: 361227
* Add TargetLoweringInfo hook for explicitly setting the ABI calling ↵Dylan McKay2019-05-211-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | convention endianess Summary: The endianess used in the calling convention does not always match the endianess of the target on all architectures, namely AVR. When an argument is too large to be legalised by the architecture and is split for the ABI, a new hook TargetLoweringInfo::shouldSplitFunctionArgumentsAsLittleEndian is queried to find the endianess that function arguments must be laid out in. This approach was recommended by Eli Friedman. Originally reported in https://github.com/avr-rust/rust/issues/129. Patch by Carl Peto. Reviewers: bogner, t.p.northover, RKSimon, niravd, efriedma Reviewed By: efriedma Subscribers: JDevlieghere, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62003 llvm-svn: 361222
* [PowerPC] use more meaningful name - NFCChen Zheng2019-05-211-6/+7
| | | | llvm-svn: 361218
* AMDGPU: Force skip branches over callsMatt Arsenault2019-05-201-1/+1
| | | | | | | | | | | | | | Unfortunately the way SIInsertSkips works is backwards, and is required for correctness. r338235 added handling of some special cases where skipping is mandatory to avoid side effects if no lanes are active. It conservatively handled asm correctly, but the same logic needs to apply to calls. Usually the call sequence code is larger than the skip threshold, although the way the count is computed is really broken, so I'm not sure if anything was likely to really hit this. llvm-svn: 361202
* [AArch64] Handle lowering lround on windows, where long is 32 bitMartin Storsjo2019-05-201-0/+4
| | | | | | Differential Revision: https://reviews.llvm.org/D62108 llvm-svn: 361192
* [AMDGPU] Fix std::array initializers to avoid warnings with older tool ↵Bjorn Pettersson2019-05-201-2/+2
| | | | | | | | | | | | | | | chains. NFC A std::array is implemented as a template with an array inside a struct. Older versions of clang, like 3.6, require an extra set of curly braces around std::array initializations to avoid warnings. The C++ language was changed regarding this by CWG 1270. So more modern tool chains does not complaing even if leaving out one level of braces. llvm-svn: 361171
* R600: Fix unconditional return in loopMatt Arsenault2019-05-201-10/+5
| | | | llvm-svn: 361167
* [AArch64][SVE2] Asm: add SADALP and UADALP instructionsCullen Rhodes2019-05-202-0/+31
| | | | | | | | | | | | | | | Summary: This patch adds support for the integer pairwise add and accumulate long instructions SADALP/UADALP. These instructions are predicated. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D62001 llvm-svn: 361154
* [DebugInfoMetadata] Refactor DIExpression::prepend constants (NFC)Petar Jovanovic2019-05-202-6/+3
| | | | | | | | | | | Refactor DIExpression::With* into a flag enum in order to be less error-prone to use (as discussed on D60866). Patch by Djordje Todorovic. Differential Revision: https://reviews.llvm.org/D61943 llvm-svn: 361137
* [AArch64][SVE2] Asm: add int halving add/sub (predicated) instructionsCullen Rhodes2019-05-202-0/+43
| | | | | | | | | | | | | | | | | | Summary: This patch adds support for the predicated integer halving add/sub instructions: * SHADD, UHADD, SRHADD, URHADD * SHSUB, UHSUB, SHSUBR, UHSUBR The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D62000 llvm-svn: 361136
* [AArch64][SVE2] Asm: add saturating multiply-add interleaved long instructionsCullen Rhodes2019-05-201-0/+4
| | | | | | | | | | | | | | Summary: Patch adds support for SQDMLALBT and SQDMLSLBT instructions. The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D61998 llvm-svn: 361135
* Use llvm::sort. NFCFangrui Song2019-05-202-2/+1
| | | | llvm-svn: 361134
* [AMDGPU] gfx1010 Avoid SMEM WAR hazard for some s_waitcnt valuesCarl Ritson2019-05-201-6/+22
| | | | | | | | | | | | | | | | | | Summary: Avoid introducing hazard mitigation when lgkmcnt is reduced to 0. Clarify code comments to explain assumptions made for this hazard mitigation. Expand and correct test cases to cover variants of s_waitcnt. Reviewers: nhaehnle, rampitec Subscribers: arsenm, kzhuravl, jvesely, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D62058 llvm-svn: 361124
* [X86] Remove combineShift function. Just dispatch directly to the handler ↵Craig Topper2019-05-191-21/+3
| | | | | | for each flavor from the main switch. NFC llvm-svn: 361108
* AMDGPU/GlobalISel: Implement s64->s64 [SU]ITOFPMatt Arsenault2019-05-172-0/+39
| | | | llvm-svn: 361082
* GlobalISel: Implement lower for S64->S32 [SU]ITOFPMatt Arsenault2019-05-171-0/+1
| | | | | | | | | | | | | This is ported from the custom AMDGPU DAG implementation. I think this is a better default expansion than what the DAG currently uses, at least if the target has CTLZ. This implements the signed version in terms of the unsigned conversion, which is implemented with bit operations. SelectionDAG has several other implementations that should eventually be ported depending on what instructions are legal. llvm-svn: 361081
* [WebAssembly] Remove expected failure of builtin-location.C testSam Clegg2019-05-171-1/+0
| | | | | | | | | | This seems to have been fixed by https://reviews.llvm.org/D61956 Yay Differential Revision: https://reviews.llvm.org/D62075 llvm-svn: 361071
* [X86][SSE] Fold movmsk(not(x)) -> not(movmsk)Simon Pilgrim2019-05-171-1/+14
| | | | | | Helps to improve folding of comparisons with movmsk results. llvm-svn: 361056
* [X86][SSE] Match all-of bool scalar reductions into a bitcast/movmsk + cmp.Simon Pilgrim2019-05-171-0/+18
| | | | | | Same as what we do for vector reductions in combineHorizontalPredicateResult, use movmsk+cmp for scalar (and(extract(x,0),extract(x,1)) reduction patterns. llvm-svn: 361052
* [AMDGPU][MC] Corrected parsing of NAME:VALUE modifiersDmitry Preobrazhensky2019-05-171-33/+17
| | | | | | | | | | See bug 41298: https://bugs.llvm.org/show_bug.cgi?id=41298 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D61009 llvm-svn: 361045
* [AMDGPU][MC] Enabled labels with s_call_b64 and s_cbranch_i_forkDmitry Preobrazhensky2019-05-171-2/+2
| | | | | | | | | | See https://bugs.llvm.org/show_bug.cgi?id=41888 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D62016 llvm-svn: 361040
* [X86][AVX] Remove LowerCTTZ's AVX1 custom vector handling.Simon Pilgrim2019-05-171-7/+0
| | | | | | We can now rely on generic expansion to handle this. llvm-svn: 361038
* [X86][AVX] isNOT - add extract_subvector(xor X, -1) -> extract_subvector(X) ↵Simon Pilgrim2019-05-171-0/+9
| | | | | | | | fold. Prep work for the removal of the remaining x86 CTTZ vector lowering. llvm-svn: 361035
* [AMDGPU][MC] Enabled expressions for most operands which accept integer valuesDmitry Preobrazhensky2019-05-172-65/+110
| | | | | | | | | | See bug 40873: https://bugs.llvm.org/show_bug.cgi?id=40873 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D60768 llvm-svn: 361031
* AMDGPU: Fix unused variable warnings in release buildsMatt Arsenault2019-05-171-12/+9
| | | | llvm-svn: 361030
* AMDGPU/GlobalISel: Legalize G_FCEILMatt Arsenault2019-05-172-2/+37
| | | | llvm-svn: 361028
* AMDGPU/GlobalISel: Legalize G_INTRINSIC_TRUNCMatt Arsenault2019-05-172-4/+70
| | | | llvm-svn: 361027
* AMDGPU/GlobalISel: Legalize G_FRINTMatt Arsenault2019-05-172-0/+44
| | | | llvm-svn: 361026
* AMDGPU/GlobalISel: Legalize G_FCOPYSIGNMatt Arsenault2019-05-171-0/+4
| | | | llvm-svn: 361025
* AMDGPU/GlobalISel: RegBankSelect for llvm.amdgcn.s.buffer.loadMatt Arsenault2019-05-171-0/+44
| | | | llvm-svn: 361023
* AMDGPU/GlobalISel: Use subreg index instead of extra unmergeMatt Arsenault2019-05-171-8/+2
| | | | | | | This saves instructions and extra steps, but I'm not sure about introducing subregister indexes at this point. llvm-svn: 361022
* AMDGPU/GlobalISel: Use waterfall loop for buffer_loadMatt Arsenault2019-05-172-36/+302
| | | | | | | This adds support for more complex waterfall loops that need to handle operands > 32-bits, and multiple operands. llvm-svn: 361021
* [X86] Pull out IsNOT helper. NFCI.Simon Pilgrim2019-05-171-8/+16
| | | | | | Return the input value for the NOT pattern: (xor X, -1) -> X llvm-svn: 361012
* [AMDGPU] detect WaW hazards when moving/merging load/store instructionsRhys Perry2019-05-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: In order to combine memory operations efficiently, the load/store optimizer might move some instructions around. It's usually safe to move instructions down past the merged instruction because the pass checks if memory operations can be re-ordered. Though, the current logic doesn't handle Write-after-Write hazards. This fixes a reflection issue with Monster Hunter World and DXVK. v2: - rebased on top of master - clean up the test case - handle WaW hazards correctly Bugzilla: https://bugs.llvm.org/show_bug.cgi?id=40130 Original patch by Samuel Pitoiset. Reviewers: tpr, arsenm, nhaehnle Reviewed By: nhaehnle Subscribers: ronlieb, arsenm, kzhuravl, jvesely, wdng, nhaehnle, yaxunl, dstuttard, tpr, t-tye Differential Revision: https://reviews.llvm.org/D61313 llvm-svn: 361008
* [AArch64][SVE2] Asm: add saturating multiply-add long instructionsCullen Rhodes2019-05-171-0/+12
| | | | | | | | | | | | | | | | | Summary: Patch adds support for indexed and unpredicated vectors forms of the following instructions: * SQDMLALB, SQDMLALT, SQDMLSLB, SQDMLSLT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: SjoerdMeijer Differential Revision: https://reviews.llvm.org/D61997 llvm-svn: 361005
* [AArch64][SVE2] Asm: add integer multiply-add long instructionsCullen Rhodes2019-05-172-0/+49
| | | | | | | | | | | | | | | | | Summary: Patch adds support for indexed and unpredicated vectors forms of the following instructions: * SMLALB, SMLALT, UMLALB, UMLALT, SMLSLB, SMLSLT, UMLSLB, UMLSLT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D61951 llvm-svn: 361003
* [AArch64][SVE2] Asm: add integer multiply long instructionsCullen Rhodes2019-05-172-0/+64
| | | | | | | | | | | | | | | | | Summary: Patch adds support for indexed and unpredicated vectors forms of the following instructions: * SMULLB, SMULLT, UMULLB, UMULLT, SQDMULLB, SQDMULLT The specification can be found here: https://developer.arm.com/docs/ddi0602/latest Reviewed By: rovka Differential Revision: https://reviews.llvm.org/D61936 llvm-svn: 361002
* [X86] Add FeatureFastScalarShiftMasks and FeatureFastVectorShiftMasks to the ↵Craig Topper2019-05-171-0/+2
| | | | | | | | | ignore list for inlining compatibility. These are tuning flags and won't cause any codegen issue if we inline a function with a different value. llvm-svn: 360992
* [PowerPC] Support .reloc *, R_PPC{,64}_NONE, *Fangrui Song2019-05-172-28/+49
| | | | | | | | This can be used to create references among sections. When --gc-sections is used, the referenced section will be retained if the origin section is retained. llvm-svn: 360990
* [MC][PowerPC] Clean up PPCAsmBackendFangrui Song2019-05-171-25/+17
| | | | | | | | Replace the member variable Target with Triple Use Triple instead of TheTarget.getName() to dispatch on 32-bit/64-bit. Delete redundant parameters llvm-svn: 360986
* [X86] Support .reloc *, R_{386,X86_64}_NONE, *Fangrui Song2019-05-172-9/+51
| | | | | | | | | | | | | | This can be used to create references among sections. When --gc-sections is used, the referenced section will be retained if the origin section is retained. See R_MIPS_NONE (D13659), R_ARM_NONE (D61992), R_AARCH64_NONE (D61973) for similar changes. Reviewed By: rnk Differential Revision: https://reviews.llvm.org/D62014 llvm-svn: 360983
* [AArch64] Support .reloc *, R_AARCH64_NONE, *Fangrui Song2019-05-172-2/+18
| | | | | | | | | | | | | Summary: This can be used to create references among sections. When --gc-sections is used, the referenced section will be retained if the origin section is retained. Reviewed By: peter.smith Differential Revision: https://reviews.llvm.org/D61973 llvm-svn: 360981
* [ARM] Support .reloc *, R_ARM_NONE, *Fangrui Song2019-05-176-9/+24
| | | | | | | | | | | | | | | | R_ARM_NONE can be used to create references among sections. When --gc-sections is used, the referenced section will be retained if the origin section is retained. Add a generic MCFixupKind FK_NONE as this kind of no-op relocation is ubiquitous on ELF and COFF, and probably available on many other binary formats. See D62014. Reviewed By: peter.smith Differential Revision: https://reviews.llvm.org/D61992 llvm-svn: 360980
* [SystemZ] Bugfix in SystemZTargetLowering::combineIntDIVREM()Jonas Paulsson2019-05-171-1/+1
| | | | | | | | | | Make sure to not unroll a vector division/remainder (with a constant splat divisor) after type legalization, since the scalar type may then be illegal. Review: Ulrich Weigand https://reviews.llvm.org/D62036 llvm-svn: 360965
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