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* [X86] Teach FCOPYSIGN lowering to recognize constant magnitudes.Ahmed Bougacha2015-01-071-6/+19
| | | | | | | | | | | | | | | | | | | | | For code like: float foo(float x) { return copysign(1.0, x); } We used to generate: andps <-0.000000e+00,0,0,0>, %xmm0 movss <1.000000e+00>, %xmm1 andps <nan>, %xmm1 orps %xmm0, %xmm1 Basically doing an abs(1.0f) in the two middle instructions. We now generate: andps <-0.000000e+00,0,0,0>, %xmm0 orps <1.000000e+00,0,0,0>, %xmm0 Builds on cleanups r223415, r223542. rdar://19049548 Differential Revision: http://reviews.llvm.org/D6555 llvm-svn: 225357
* Fix regression in r225266.Asiri Rathnayake2015-01-071-1/+1
| | | | | | | | The change in r225266 was reviewed under D6722. But the commit r225266 has a typo, causing some MCHammer failures. This patch fixes it. Change-Id: I573efcff25003af7478ac02548ebbe929fc7f5fd llvm-svn: 225347
* [X86] Merge a switch statement inside a default case of another switch ↵Craig Topper2015-01-071-160/+155
| | | | | | statement on the same variable. There was no additional code in the default so this should be no functional change. llvm-svn: 225345
* [X86] Don't mark the shift by 1 instructions as isConvertibleToThreeAddress. ↵Craig Topper2015-01-071-1/+1
| | | | | | There is no handling for them. llvm-svn: 225344
* [X86] Remove some unused TYPE enums from the disassembler.Craig Topper2015-01-073-18/+1
| | | | llvm-svn: 225343
* Revert r225165 and r225169Karthik Bhat2015-01-071-39/+0
| | | | | | | | Even thouh gcc produces simialr instructions as Owen pointed out the two patterns aren’t equivalent in the case where the original subtraction could have caused an overflow. Reverting the same. llvm-svn: 225341
* R600/SI: Add check for amdgcn triple forgotten in r225276.Tom Stellard2015-01-071-2/+3
| | | | llvm-svn: 225331
* [PowerPC] Transform a README.txt entry into a FIXMEHal Finkel2015-01-072-14/+9
| | | | | | | | | | Remove the README.txt entry regarding register allocation of CR logical ops, and replace it with a FIXME in PPCInstrInfo.td. The text in the README.txt was not really accurate, and thanks goes to Pat Haugen (and Bill Schmidt) from IBM for clarifying what was intended and highlighting the relevant text in the ISA specification. llvm-svn: 225325
* Revert r224935 "Refactor duplicated code. No intended functionality change."Lang Hames2015-01-066-8/+30
| | | | | | | | This is affecting the behavior of some ObjC++ / AArch64 test cases on Darwin. Reverting to get the bots green while I track down the source of the changed behavior. llvm-svn: 225311
* R600/SI: Add combine for isinfinite patternMatt Arsenault2015-01-062-0/+57
| | | | llvm-svn: 225310
* R600/SI: Pattern match isinf to v_cmp_class instructionsMatt Arsenault2015-01-062-0/+34
| | | | llvm-svn: 225307
* R600/SI: Add basic DAG combines for fp_classMatt Arsenault2015-01-062-1/+50
| | | | llvm-svn: 225306
* R600/SI: Add class intrinsicMatt Arsenault2015-01-067-5/+82
| | | | llvm-svn: 225305
* [PowerPC] Reuse a load operand in int->fp conversionsHal Finkel2015-01-063-41/+142
| | | | | | | | | | | | | | | | | | | | | | | int->fp conversions on PPC must be done through memory loads and stores. On a modern core, this process begins by storing the int value to memory, then loading it using a (sometimes special) FP load instruction. Unfortunately, we would do this even when the value to be converted was itself a load, and we can just use that same memory location instead of copying it to another first. There is a slight complication when handling int_to_fp(fp_to_int(x)) pairs, because the fp_to_int operand has not been lowered when the int_to_fp is being lowered. We handle this specially by invoking fp_to_int's lowering logic (partially) and getting the necessary memory location (some trivial refactoring was done to make this possible). This is all somewhat ugly, and it would be nice if some later CodeGen stage could just clean this stuff up, but because doing so would involve modifying target-specific nodes (or instructions), it is not immediately clear how that would work. Also, remove a related entry from the README.txt for which we now generate reasonable code. llvm-svn: 225301
* [Hexagon] Adding compound jump encodings.Colin LeMahieu2015-01-062-0/+266
| | | | llvm-svn: 225291
* R600/SI: Insert s_waitcnt before s_barrier instructions.Tom Stellard2015-01-061-1/+5
| | | | | | | This ensures that all memory operations are complete when all threads reach the barrier. llvm-svn: 225290
* R600/SI: Fix dependency calculation for DS writes instructions in SIInsertWaitsTom Stellard2015-01-061-0/+23
| | | | | | | | | | | | In DS write instructions, the address operand comes before the value operand(s) which is reversed from every other instruction type. The SIInsertWait assumed that the first use for each instruction was the value, so for DS write it was protecting the address operand with s_waitcnt instructions when it should have been protecting the value operand. llvm-svn: 225289
* [Hexagon] Adding encoding for misc v4 instructions: boundscheck, tlbmatch, ↵Colin LeMahieu2015-01-063-1/+101
| | | | | | dcfetch. llvm-svn: 225283
* [Hexagon] Adding encoding information for absolute address loads.Colin LeMahieu2015-01-061-124/+186
| | | | llvm-svn: 225279
* R600/SI: Add a stub GCNTargetMachineTom Stellard2015-01-068-1/+46
| | | | | | | | | | | | This is equivalent to the AMDGPUTargetMachine now, but it is the starting point for separating R600 and GCN functionality into separate targets. It is recommened that users start using the gcn triple for GCN-based GPUs, because using the r600 triple for these GPUs will be deprecated in the future. llvm-svn: 225277
* R600/SI: Remove MachineFunction dump from AsmPrinterTom Stellard2015-01-061-17/+12
| | | | | | | The dump was dependent on a feature string, which meant that it couldn't be disabled or enable on a per compile basis. llvm-svn: 225275
* [Hexagon] Fix 225267. GP register is not yet fully implemented. Removing ↵Colin LeMahieu2015-01-061-2/+2
| | | | | | Uses [GP] maintains existing behavior. llvm-svn: 225270
* [Hexagon] Adding dealloc_return encoding and absolute address stores.Colin LeMahieu2015-01-065-239/+347
| | | | llvm-svn: 225267
* [ARM] Cleanup so_imm* tblgen defintionsAsiri Rathnayake2015-01-062-109/+43
| | | | | | | | | | | No functional changes. Support for ARM's modified immediate syntax was added in r223113 and r223115 (review: D6408). That patch introduced the mod_imm* tblegen definitions which renders the existing so_imm* definitions redundant. This patch gets rid of them completely. Reviewed as: D6722 llvm-svn: 225266
* [X86] Add OpSize32 to XBEGIN_4. Add XBEGIN_2 with OpSize16.Craig Topper2015-01-064-7/+40
| | | | | | Requires new AsmParserOperand types that detect 16-bit and 32/64-bit mode so that we choose the right instruction based on default sizing without predicates. This is necessary since predicates mess up the disassembler table building. llvm-svn: 225256
* [X86] Make isel select the 2-byte register form of INC/DEC even in ↵Craig Topper2015-01-065-126/+78
| | | | | | | | non-64-bit mode. Convert to the 1-byte form in non-64-bit mode as part of MCInst lowering. Overall this seems simpler. It reduces duplication of patterns between both modes and it simplifies the memory folding/unfolding tables as they don't need to create fake instructions just to keep track of 64-bitness. llvm-svn: 225252
* [PowerPC] Remove old README.txt entry regarding struct passingHal Finkel2015-01-061-8/+0
| | | | | | | Because of how Clang represents structs as arrays (at least on non-Darwin platforms), and what SROA does, etc. this is no longer a problem. llvm-svn: 225251
* X86: Don't make illegal GOTTPOFF relocationsDavid Majnemer2015-01-062-0/+17
| | | | | | | | | | | | | "ELF Handling for Thread-Local Storage" specifies that R_X86_64_GOTTPOFF relocation target a movq or addq instruction. Prohibit the truncation of such loads to movl or addl. This fixes PR22083. Differential Revision: http://reviews.llvm.org/D6839 llvm-svn: 225250
* [PowerPC] Add some missing names in getTargetNodeNameHal Finkel2015-01-061-0/+7
| | | | | | These are used for debugging output; NFC. llvm-svn: 225249
* [PowerPC] Improve int_to_fp(fp_to_int(x)) combiningHal Finkel2015-01-062-30/+74
| | | | | | | | | The old target DAG combine that allowed for performing int_to_fp(fp_to_int(x)) without a load/store pair is updated here with support for unsigned integers, and to support single-precision values without a third rounding step, on newer cores with the appropriate instructions. llvm-svn: 225248
* [X86] Remove 16-bit and 32-bit offset jump instructions from the AsmParser. ↵Craig Topper2015-01-061-2/+2
| | | | | | We always select the 8-bit size and let the assembler backend relax to the larger size. llvm-svn: 225243
* [X86] Make isel select the shorter form of jump instructions instead of the ↵Craig Topper2015-01-068-120/+97
| | | | | | | | long form. The assembler backend will relax to the long form if necessary. This removes a swap from long form to short form in the MCInstLowering code. Selecting the long form used to be required by the old JIT. llvm-svn: 225242
* Remove dead variable.Eric Christopher2015-01-062-2/+1
| | | | llvm-svn: 225233
* Use the same call off of the TargetMachine rather than the subtarget.Eric Christopher2015-01-061-1/+1
| | | | llvm-svn: 225232
* Rewrite the Mips16HardFloat pass to avoid using the Subtarget.Eric Christopher2015-01-064-26/+18
| | | | llvm-svn: 225231
* Revert r225048: It broke ObjC on AArch64.Lang Hames2015-01-067-102/+182
| | | | | | I've filed http://llvm.org/PR22100 to track this issue. llvm-svn: 225228
* Remove X86 .quad workaround for buggy GNU assembler on OpenBSD / Bitrig.Brad Smith2015-01-061-5/+0
| | | | llvm-svn: 225227
* Revert "Use the integrated assembler by default on 32-bit PowerPC and SPARC"Duncan P. N. Exon Smith2015-01-052-2/+4
| | | | | | | | | This reverts commit r225213. It's failing on multiple buildbots [1][2]. [1]: http://lab.llvm.org:8011/builders/clang-x86_64-debian-fast/builds/22032 [2]: http://lab.llvm.org:8080/green/view/Clang/job/clang-stage1-cmake-RA-incremental_check/2357/ llvm-svn: 225222
* [PowerPC] Remove old README.txt entryHal Finkel2015-01-051-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | We no longer generate horrible code for the stated function: void f(signed char *a, _Bool b, _Bool c) { signed char t = 0; if (b) t = *a; if (c) *a = t; } for which we now generate: .L.f: andi. 5, 5, 1 cmpldi 1, 4, 0 li 5, 0 beq 1, .LBB0_2 lbz 5, 0(3) .LBB0_2: # %if.end bclr 4, 1, 0 stb 5, 0(3) blr so we don't need the README.txt entry. llvm-svn: 225217
* [X86][SSE] lowerVectorShuffleAsByteShift tidyupSimon Pilgrim2015-01-051-21/+14
| | | | | | Removed local isSequential predicate and use standard helper isSequentialOrUndefInRange instead. llvm-svn: 225216
* [PowerPC] Convert a README.txt entry into a better testHal Finkel2015-01-051-13/+0
| | | | | | | We now produce the desired code as noted in the README.txt file (no spurious or). Remove the README entry and improve the regression test. llvm-svn: 225214
* Use the integrated assembler by default on 32-bit PowerPC and SPARCBrad Smith2015-01-052-4/+2
| | | | llvm-svn: 225213
* [PowerPC] Remove README.txt entryHal Finkel2015-01-051-34/+0
| | | | | | | This entry has been rendered irrelevant now that we have proper CR bit tracking. llvm-svn: 225211
* [Hexagon] Adding add/sub with carry, logical shift left by immediate and ↵Colin LeMahieu2015-01-052-226/+124
| | | | | | memop instructions. Removing old defs without bits and updating references. llvm-svn: 225210
* [PowerPC] Add a test for truncating a shifted loadHal Finkel2015-01-051-18/+0
| | | | | | | We now produce the desired code as noted in the README.txt file. Remove the README entry and add a regression test. llvm-svn: 225209
* [PowerPC] Add another test for load/store with updateHal Finkel2015-01-051-34/+0
| | | | | | | We now produce the desired code as noted in the README.txt file. Remove the README entry and add a regression test. llvm-svn: 225205
* [PowerPC] Fold i1 extensions with other opsHal Finkel2015-01-052-17/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Consider this function from our README.txt file: int foo(int a, int b) { return (a < b) << 4; } We now explicitly track CR bits by default, so the comment in the README.txt about not really having a SETCC is no longer accurate, but we did generate this somewhat silly code: cmpw 0, 3, 4 li 3, 0 li 12, 1 isel 3, 12, 3, 0 sldi 3, 3, 4 blr which generates the zext as a select between 0 and 1, and then shifts the result by a constant amount. Here we preprocess the DAG in order to fold the results of operations on an extension of an i1 value into the SELECT_I[48] pseudo instruction when the resulting constant can be materialized using one instruction (just like the 0 and 1). This was not implemented as a DAGCombine because the resulting code would have been anti-canonical and depends on replacing chained user nodes, which does not fit well into the lowering paradigm. Now we generate: cmpw 0, 3, 4 li 3, 0 li 12, 16 isel 3, 12, 3, 0 blr which is less silly. llvm-svn: 225203
* [X86][SSE] Fixed description for isSequentialOrUndefInRange. NFC.Simon Pilgrim2015-01-051-1/+1
| | | | llvm-svn: 225202
* [Hexagon] Adding rounding reg/reg variants, accumulating multiplies, and ↵Colin LeMahieu2015-01-051-57/+170
| | | | | | accumulating shifts. llvm-svn: 225201
* [Hexagon] Adding V4 bit manipulating instructions, removing ALU defs without ↵Colin LeMahieu2015-01-051-251/+104
| | | | | | encoding bits. llvm-svn: 225199
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