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* [AArch64] Disable narrow load merge by defaultJun Bum Lim2016-05-201-1/+1
| | | | | | | | | | | | | | Summary: As this optimization converts two loads into one load with two shift instructions, it could potentially hurt performance if a loop is arithmetic operation intensive. Reviewers: t.p.northover, mcrosier, jmolloy Subscribers: evandro, jmolloy, aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D20172 llvm-svn: 270251
* [X86] Reduce memory allocations in X86TargetMachine::getSubtargetImplDavid Majnemer2016-05-203-10/+15
| | | | | | | | We performed a number of memory allocations each time getTTI was called, remove them by using SmallString. No functionality change intended. llvm-svn: 270246
* fix comments; NFCSanjay Patel2016-05-201-9/+8
| | | | llvm-svn: 270237
* use range-loops; NFCISanjay Patel2016-05-201-4/+2
| | | | llvm-svn: 270236
* fix documentation comments; NFCSanjay Patel2016-05-201-9/+8
| | | | llvm-svn: 270234
* [X86][AVX] Generalized matching for target shuffle combinesSimon Pilgrim2016-05-201-99/+146
| | | | | | | | | | | | This patch is a first step towards a more extendible method of matching combined target shuffle masks. Initially this just pulls out the existing basic mask matches and adds support for some 256/512 bit equivalents. Future patterns will require a number of features to be added but I wanted to keep this patch simple. I hope we can avoid duplication between shuffle lowering and combining and share more complex pattern match functions in future commits. Differential Revision: http://reviews.llvm.org/D19198 llvm-svn: 270230
* Refactor X86 symbol access classification.Rafael Espindola2016-05-204-155/+130
| | | | | | | | | | | | This refactors the logic in X86 to avoid code duplication. It also splits it in two steps: it first decides if a symbol is local to the DSO and then uses that information to decide how to access it. The first part is implemented by shouldAssumeDSOLocal. It is not in any way specific to X86. In a followup patch I intend to move it to somewhere common and reused it in other backends. llvm-svn: 270209
* Simplify handling of hidden stubs on PowerPC.Rafael Espindola2016-05-202-25/+4
| | | | | | | We now handle them just like non hidden ones. This was already the case on x86 (r207518) and arm (r207517). llvm-svn: 270205
* SparcISelLowering.cpp: Add missing StringSwitch.hNAKAMURA Takumi2016-05-201-0/+1
| | | | llvm-svn: 270200
* [Sparc] Implement getRegisterByName.Chris Dewhurst2016-05-202-0/+24
| | | | | | Allows Sparc registers to be specifically referred to in inline assembly. llvm-svn: 270198
* [Sparc] Enable more inline assembly constraints.Chris Dewhurst2016-05-202-0/+9
| | | | | | | | Note: This is specifically to allow GCC's test pr44707 to pass. Trivial change, not put for differential revision. Test included. llvm-svn: 270192
* [X86] Fix another AVX pattern to only be disable if VLX and BWI are supported.Craig Topper2016-05-201-1/+1
| | | | llvm-svn: 270182
* [lanai] Use Optional<Reloc> in LanaiTargetMachine.Jacques Pienaar2016-05-204-12/+17
| | | | | | Follow r269988 and use Optional<Reloc>. llvm-svn: 270176
* [X86] Fix some AVX patterns to only be disabled if VLX and BWI are ↵Craig Topper2016-05-201-20/+24
| | | | | | supported. Without this we get isel failures on the avx-intrinsics-x86.ll test in AVX512VL. llvm-svn: 270174
* Add AVRTargetStreamersDylan McKay2016-05-205-0/+147
| | | | | | Reviewed by Matt Arsenault in http://reviews.llvm.org/D16311 llvm-svn: 270171
* Record a TargetMachine instead of a Reloc::Model.Rafael Espindola2016-05-194-16/+13
| | | | | | Addresses r270095's code review. llvm-svn: 270147
* AMDGPU: Remove pointless conversionsMatt Arsenault2016-05-191-30/+10
| | | | llvm-svn: 270139
* [WebAssembly] Simplify code that never has to handle physical registers. NFC.Dan Gohman2016-05-191-9/+2
| | | | llvm-svn: 270137
* Fix -Wunused-variable in non-Asserts buildDavid Blaikie2016-05-191-2/+1
| | | | llvm-svn: 270118
* Simplify conditional unreachable into an assertionDavid Blaikie2016-05-191-7/+3
| | | | llvm-svn: 270111
* X86: Don't reset the stack after calls that don't return (PR27117)Hans Wennborg2016-05-191-0/+6
| | | | | | | | | Since the calls don't return, the instruction afterwards will never run, and is just taking up unnecessary space in the binary. Differential Revision: http://reviews.llvm.org/D20406 llvm-svn: 270109
* Remember the relocation model. NFC.Rafael Espindola2016-05-195-18/+16
| | | | | | This avoids passing a TargetMachine in a few places. llvm-svn: 270095
* Style fixes. NFC.Rafael Espindola2016-05-195-18/+16
| | | | llvm-svn: 270093
* [SystemZ] Test commit - remove idea from READMEZhan Jun Liau2016-05-191-5/+0
| | | | | | | Remove a comment about not supporting LRVH/STRVH from the README LRVH/STRVH are being generated as of r269688 llvm-svn: 270092
* AMDGPU: Also look for s_cbranch_vcczMatt Arsenault2016-05-191-1/+2
| | | | llvm-svn: 270091
* Fix a covnersion from string to bool issue used in an assertRon Lieberman2016-05-191-1/+1
| | | | | | | Problem Was exposed by -Wstring-conversion llvm-svn: 270087
* [AArch64 ] Generate a BFXIL from 'or (and X, Mask0Imm),(and Y, Mask1Imm)'.Chad Rosier2016-05-191-0/+59
| | | | | | | | | | | | | | | | | | Mask0Imm and ~Mask1Imm must be equivalent and one of the MaskImms is a shifted mask (e.g., 0x000ffff0). Both 'and's must have a single use. This changes code like: and w8, w0, #0xffff000f and w9, w1, #0x0000fff0 orr w0, w9, w8 into lsr w8, w1, #4 bfi w0, w8, #4, #12 llvm-svn: 270063
* Test commit.Ranjeet Singh2016-05-191-1/+1
| | | | llvm-svn: 270056
* [AMDGPU][llvm-mc] Fixes to support buffer atomics.Artem Tamazov2016-05-192-11/+88
| | | | | | | | | | | | Fixes for MUBUF_Atomic instructions to make operand list valid: - For RTN insns, make a copy of $vdata_in operand as $vdata. - Do not add operand for GLC, it is hardcoded and comes as a token. Workaround to avoid adding multiple default optional operands. Tests added. Differential Revision: http://reviews.llvm.org/D20257 llvm-svn: 270049
* ps][microMIPS] Add R_MICROMIPS_PC21_S1 relocationZoran Jovanovic2016-05-194-3/+21
| | | | | | Differential Revision: http://reviews.llvm.org/D15526 llvm-svn: 270048
* [mips][mips16] Fix ZERO is not a CPU16Regs register error from the machine ↵Daniel Sanders2016-05-191-1/+1
| | | | | | | | | | | | | | verifier. Summary: Partially fixes PR27458 Reviewers: sdardis Subscribers: dsanders, llvm-commits, sdardis Differential Revision: http://reviews.llvm.org/D20330 llvm-svn: 270037
* [X86] Enable RRL part of the LEA optimization pass for -O2.Andrey Turetskiy2016-05-191-10/+8
| | | | | | | | | | Enable "Remove Redundant LEAs" part of the LEA optimization pass for -O2. This gives 6.4% performance improve on Broadwell on nnet benchmark from Coremark-pro. There is no significant effect on other benchmarks (Geekbench, Spec2000, Spec2006). Differential Revision: http://reviews.llvm.org/D19659 llvm-svn: 270036
* [mips][microMIPS] Implement BC1EQZC, BC1NEZC, BC2EQZC and BC2NEZC instructionsZlatko Buljan2016-05-194-4/+55
| | | | | | Differential Revision: http://reviews.llvm.org/D18352 llvm-svn: 270030
* [X86] Generalize and combine some similar type constraints and node types. ↵Craig Topper2016-05-192-88/+57
| | | | | | No changes to the isel table size so the separation wasn't buying us anything. llvm-svn: 270026
* [X86] Simplify some type constraints by removing parts that were already ↵Craig Topper2016-05-191-12/+5
| | | | | | implied. llvm-svn: 270025
* [WebAssembly] Update WebAssembly target for r269988.Dan Gohman2016-05-192-4/+11
| | | | llvm-svn: 270017
* [X86] Remove some type constraint classes and use already existing stricter ↵Craig Topper2016-05-191-16/+10
| | | | | | classes. llvm-svn: 270013
* [AVX512] Strengthen type constraints for VFIXUPIMM patterns and combine the ↵Craig Topper2016-05-191-7/+8
| | | | | | type constraints for vector and scalar. llvm-svn: 270012
* [AArch64] Push comment into function. NFC.Chad Rosier2016-05-181-9/+9
| | | | llvm-svn: 270003
* AMDGPU: Fix verifier error when spilling undef subregMatt Arsenault2016-05-181-3/+11
| | | | llvm-svn: 270002
* AMDGPU: Fix promote alloca for pointer loadsMatt Arsenault2016-05-181-3/+7
| | | | | | | If the load has a pointer type, we don't want to change its type. llvm-svn: 270000
* Delete Reloc::Default.Rafael Espindola2016-05-1837-181/+270
| | | | | | | | | | | | Having an enum member named Default is quite confusing: Is it distinct from the others? This patch removes that member and instead uses Optional<Reloc> in places where we have a user input that still hasn't been maped to the default value, which is now clear has no be one of the remaining 3 options. llvm-svn: 269988
* [lanai] Change the way flag setting instructions are checked.Jacques Pienaar2016-05-181-51/+11
| | | | | | | | isReturn() was returning different values with and without -g which led to different code being generated. Change isFlagSettingInstruction to query an instruction's effect on SR instead. llvm-svn: 269986
* [WebAssembly] Disable the MachineScheduler.Dan Gohman2016-05-182-1/+14
| | | | llvm-svn: 269976
* AMDGPU: Fix incorrect simm checkJan Vesely2016-05-181-1/+1
| | | | | | | | | Use signed division otherwise all back jumps fail the check Fixes regression introduced in r269951 Differential Revision: http://reviews.llvm.org/D20380 llvm-svn: 269972
* [AArch64] Minor refactoring. NFC.Chad Rosier2016-05-181-4/+5
| | | | llvm-svn: 269963
* clean up; NFCISanjay Patel2016-05-181-5/+4
| | | | llvm-svn: 269962
* AMDGPU: Error if branch distance exceeds limitMatt Arsenault2016-05-181-1/+5
| | | | llvm-svn: 269951
* AMDGPU: Other sizes of popcnt are fastMatt Arsenault2016-05-181-1/+1
| | | | | | | We can chain bcnt instructions together, so any width popcnt is pretty fast. llvm-svn: 269950
* Re-commit r269828 "X86: Avoid using _chkstk when lowering WIN_ALLOCA ↵Hans Wennborg2016-05-189-38/+332
| | | | | | | | | | | | instructions" with an additional fix to make RegAllocFast ignore undef physreg uses. It would previously get confused about the "push %eax" instruction's use of eax. That method for adjusting the stack pointer is used in X86FrameLowering::emitSPUpdate as well, but since that runs after register-allocation, we didn't run into the RegAllocFast issue before. llvm-svn: 269949
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