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* AMDGPU: Fix assert when erroring on a callMatt Arsenault2016-05-181-1/+5
| | | | | | | For some reason an assert is now hit when a valid chain is not returned, so return the entry chain. llvm-svn: 269948
* Trivial cleanups.Rafael Espindola2016-05-1811-22/+22
| | | | | | | This just clang formats and cleans comments in an area I am about to post a patch for review. llvm-svn: 269946
* AMDGPU: Handle alloca promoting with null operandsMatt Arsenault2016-05-181-2/+37
| | | | | | | If the second pointer in a multi-pointer instruction is a constant, we can replace the type. llvm-svn: 269945
* AMDGPU: Don't run passes that aren't usefulMatt Arsenault2016-05-181-0/+5
| | | | llvm-svn: 269943
* AMDGPU: Fix assert on ttmp registersMatt Arsenault2016-05-181-2/+2
| | | | | | | | | | | Use register class that does not include them when looking for unallocated registers. This is hit by the udiv v8i64 test in the opencl integer conformance test, and takes a few seconds to compile in a debug build so no test included. llvm-svn: 269938
* [Hexagon] Recognize "q" and "v" in inline-asm as register constraintsKrzysztof Parzyszek2016-05-182-2/+16
| | | | llvm-svn: 269933
* [WebAssembly] Don't expand divisions by constants.Dan Gohman2016-05-182-0/+7
| | | | | | | Don't expand divisions by constants if it would require multiple instructions. The current assumption is that engines will perform the desired optimizations. llvm-svn: 269930
* [SystemZ] Fix register ordering for BinaryRRF instructionsBryan Chan2016-05-181-2/+2
| | | | | | | | | | | | | | | | | Summary: The ordering of registers in BinaryRRF instructions are wrong, and affects the copysign instruction (CPSDR). This results in the wrong magnitude and sign being set. Author: zhanjunl Reviewers: kbarton, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D20308 llvm-svn: 269922
* Add new flag and intrinsic support for MWAITX and MONITORX instructionsAshutosh Nema2016-05-187-15/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: MONITORX/MWAITX instructions provide similar capability to the MONITOR/MWAIT pair while adding a timer function, such that another termination of the MWAITX instruction occurs when the timer expires. The presence of the MONITORX and MWAITX instructions is indicated by CPUID 8000_0001, ECX, bit 29. The MONITORX and MWAITX instructions are intercepted by the same bits that intercept MONITOR and MWAIT. MONITORX instruction establishes a range to be monitored. MWAITX instruction causes the processor to stop instruction execution and enter an implementation-dependent optimized state until occurrence of a class of events. Opcode of MONITORX instruction is "0F 01 FA". Opcode of MWAITX instruction is "0F 01 FB". These opcode information is used in adding tests for the disassembler. These instructions are enabled for AMD's bdver4 architecture. Patch by Ganesh Gopalasubramanian! Reviewers: echristo, craig.topper, RKSimon Subscribers: RKSimon, joker.eph, llvm-commits Differential Revision: http://reviews.llvm.org/D19795 llvm-svn: 269911
* Don't pass a Reloc::Model to MC.Rafael Espindola2016-05-185-8/+7
| | | | | | | | | | | | MC only needs to know if the output is PIC or not. It never has to decide about creating GOTs and PLTs for example. The only thing that MC itself uses this information for is expanding "macros" in sparc and mips. The rest I am pretty sure could be moved to CodeGen. This is a cleanup and isolates the code from future changes to Reloc::Model. llvm-svn: 269909
* [AVR] Remove the 'AVRConfig.h' headerDylan McKay2016-05-187-27/+0
| | | | | | | | | | It defined the LLVM_AVR_GCC_COMPAT constant, which would enable/disable certain GCC-specific behaviours. There is no point conditionally turning it on/off, as it will always be turned on, and we have to maintain both code paths anyway. llvm-svn: 269904
* [AVR] Add missing CMake dependenciesDylan McKay2016-05-182-6/+8
| | | | llvm-svn: 269901
* [AVR] Fix a few compile errorsDylan McKay2016-05-183-5/+4
| | | | llvm-svn: 269900
* [PATCH] [mips] Restrict the creation of compact branchesSimon Dardis2016-05-184-2/+47
| | | | | | | | | | | | | | | | | Restrict the creation of compact branches so that they do meet the ISA requirements. Notably do not permit $zero to be used as a operand for compact branches and ensure that some other branches fulfil the requirement that rs != rt. Fixup cases where $rs > $rt for bnec and beqc. Recommit of rL269893 with reviewers comments. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D20284 llvm-svn: 269899
* Revert "[mips] Restrict the creation of compact branches"Simon Dardis2016-05-184-47/+2
| | | | | | | | This reverts commit rL269893. Incorrect patch applied. llvm-svn: 269897
* [AVR] Convert C style comments to C++Dylan McKay2016-05-187-27/+11
| | | | llvm-svn: 269895
* [mips] Restrict the creation of compact branchesSimon Dardis2016-05-184-2/+47
| | | | | | | | | | | | | | | Restrict the creation of compact branches so that they meet the ISA encoding requirements. Notably do not permit $zero to be used as a operand for compact branches and ensure that some other branches fulfil the requirement that rs != rt. Fixup cases where $rs > $rt for bnec and beqc. Reviewers: dsanders, vkalintiris Differential Review: http://reviews.llvm.org/D20284 llvm-svn: 269893
* [Sparc] Add Soft Float supportChris Dewhurst2016-05-187-12/+59
| | | | | | | | | | This change adds support for software floating point operations for Sparc targets. This is the first in a set of patches to enable software floating point on Sparc. The next patch will enable the option to be used with Clang. Differential Revision: http://reviews.llvm.org/D19265 llvm-svn: 269892
* [AVX512] Strengthen type constraints on my rounding mode inputs and some ↵Craig Topper2016-05-181-16/+23
| | | | | | immediate inputs. llvm-svn: 269886
* [AVX512] Strengthen type checks on the X86ISD::SELECT node. Saves over 800 ↵Craig Topper2016-05-182-6/+16
| | | | | | bytes in the DAG isel table by removing type checks for the condition operand which is always a vector or scalar of i1 matching the the number of elements in the other operands. llvm-svn: 269885
* [mips][microMIPS] Implement LH, LHE, LHU and LHUE instructions and add ↵Zlatko Buljan2016-05-184-18/+41
| | | | | | | | CodeGen support Differential Revision: http://reviews.llvm.org/D15418 llvm-svn: 269883
* [WebAssembly] Rename $discard to $drop in the assembly output.Dan Gohman2016-05-174-13/+12
| | | | llvm-svn: 269862
* [WebAssembly] Model the stack evaluation order more precisely.Dan Gohman2016-05-171-20/+40
| | | | | | | | | | | We currently don't represent get_local and set_local explicitly; they are just implied by virtual register use and def. This avoids a lot of clutter, but it does complicate stackifying: get_locals read their operands at their position in the stack evaluation order, rather than at their parent instruction. This patch adds code to walk the stack to determine the precise ordering, when needed. llvm-svn: 269854
* [WebAssembly] Don't stackify calls past stack pointer modifications.Dan Gohman2016-05-172-20/+41
| | | | llvm-svn: 269843
* Revert r269828 "X86: Avoid using _chkstk when lowering WIN_ALLOCA instructions"Hans Wennborg2016-05-179-332/+38
| | | | | | Seems to have broken the Windows ASan bot. Reverting while investigating. llvm-svn: 269833
* [WebAssembly] Stackify induction variable increment instructions.Dan Gohman2016-05-171-28/+65
| | | | | | | This handles instructions where the defined register is also used, as in "x = x + 1". llvm-svn: 269830
* X86: Avoid using _chkstk when lowering WIN_ALLOCA instructionsHans Wennborg2016-05-179-38/+332
| | | | | | | | | | | | | | | This patch moves the expansion of WIN_ALLOCA pseudo-instructions into a separate pass that walks the CFG and lowers the instructions based on a conservative estimate of the offset between the stack pointer and the lowest accessed stack address. The goal is to reduce binary size and run-time costs by removing calls to _chkstk. While it doesn't fix all the code quality problems with inalloca calls, it's an incremental improvement for PR27076. Differential Revision: http://reviews.llvm.org/D20263 llvm-svn: 269828
* Simplify handling of hidden stub.Rafael Espindola2016-05-177-67/+6
| | | | | | | | | Since r207518 they are printed exactly like non-hidden stubs on x86 and since r207517 on ARM. This means we can use a single set for all stubs in those platforms. llvm-svn: 269776
* [ARM] ARM mov InstAlias for MOVW lacks HasV6T2Renato Golin2016-05-171-1/+1
| | | | | | | | | | | | | | The movw instruction is only available in ARM state for V6T2 and above. The MOVi16 instruction has requirement HasV6T2 but the InstAlias for mov rd, imm where the operand is imm0_65535_expr:$imm does not. This means that movw can incorrectly be used in ARMv4 and ARMv5 by writing mov rd, 0x1234. The simple fix is to the requirement HasV6T2 to the InstAlias. Tests added to not-armv4.s. Patch by Peter Smith. llvm-svn: 269761
* Fix for PR27750. Correctly handle the case where the fallthrough block andDavid L Kreitzer2016-05-171-5/+9
| | | | | | | | target block are the same in getFallThroughMBB. Differential Revision: http://reviews.llvm.org/D20288 llvm-svn: 269760
* [WebAssembly] Remove our copy of PrologEpilogInserterDerek Schuff2016-05-173-1060/+0
| | | | | | It's no longer needed after r269750 llvm-svn: 269756
* [mips][microMIPS] Implement BEQZC and BNEZC instructionsZoran Jovanovic2016-05-176-3/+77
| | | | | | Differential Revision: http://reviews.llvm.org/D15417 llvm-svn: 269755
* [mips] Compact branch policy control for MIPSR6Simon Dardis2016-05-171-8/+34
| | | | | | | | | | | | | | | This patch adds the commandline option -mips-compact-branches={never,optimal,always), which controls how LLVM generates compact branches for MIPS targets. By default, the compact branch policy is 'optimal' where LLVM will (hopefully) pick the optimal branch for any situation. The 'never' policy will disable the generation of compact branches and 'always' will generate compact branches wherever possible. Reviewers: dsanders Differential Review: http://reviews.llvm.org/D20167 llvm-svn: 269753
* [mips][microMIPS][DSP] Implement BALIGN, BITREV, BPOSGE32, CMP*, CMPGDU*, ↵Zlatko Buljan2016-05-173-19/+124
| | | | | | | | CMPGU* and CMPU* instructions Differential Revision: http://reviews.llvm.org/D16182 llvm-svn: 269752
* Factor PrologEpilogInserter around spilling, frame finalization, and scavengingDerek Schuff2016-05-172-8/+2
| | | | | | | | | | | | | | | PrologEpilogInserter has these 3 phases, which are related, but not all of them are needed by all targets. This patch reorganizes PEI's varous functions around those phases for more clear separation. It also introduces a new TargetMachine hook, usesPhysRegsForPEI, which is true for non-virtual targets. When it is true, all the phases operate as before, and PEI requires the AllVRegsAllocated property on MachineFunctions. Otherwise, CSR spilling and scavenging are skipped and only prolog/epilog insertion/frame finalization is done. Differential Revision: http://reviews.llvm.org/D18366 llvm-svn: 269750
* [WebAssembly] Improve the precision of memory and side effect dependence ↵Dan Gohman2016-05-171-23/+192
| | | | | | | | | | tracking. MachineInstr::isSafeToMove is more conservative than is needed here; use a more explicit check, and incorporate knowledge of some WebAssembly-specific opcodes. llvm-svn: 269736
* AMDGPU/R600: Use correct number of vector elements when lowering private loadsJan Vesely2016-05-161-5/+3
| | | | | | | | | | Reviewer: tstellardAMD, arsenm Subscribers: arsenm, kzhuravl, llvm-commits Differential Revision: http://reviews.llvm.org/D20032 llvm-svn: 269725
* AMDGPU: Fix promote alloca pass creating huge arraysMatt Arsenault2016-05-163-20/+154
| | | | | | | | | | | | | | | This was assuming it could use all memory before, which is a bad decision because it restricts occupancy. By default, only try to use enough space that could reduce occupancy to 7, an arbitrarily chosen limit. Based on the exist LDS usage, try to round up to the limit in the current tier instead of further hurting occupancy. This isn't ideal, because it doesn't accurately know how much space is going to be used for alignment padding. llvm-svn: 269708
* [AArch64] Fix bug in large stack spill slot handling (PR27717)Geoff Berry2016-05-161-1/+3
| | | | | | | | | | | | | | | | | Summary: Fix bug in MachO path where a frame index offset would not be reserved for handling large frames when an extra non-used callee-save register was saved. In the case where the extra register is reserved or not a GPR (e.g. %FP in the MachO case), this would lead to the register scavenger later failing when called from PrologEpilogInserter. Reviewers: t.p.northover Subscribers: aemerson, rengolin, mcrosier, llvm-commits Differential Revision: http://reviews.llvm.org/D20185 llvm-svn: 269697
* [SystemZ] Support LRVH and STRVH opcodesBryan Chan2016-05-164-5/+114
| | | | | | | | | | | | Summary: On Linux, /usr/include/bits/byteswap-16.h defines __byteswap_16(x) as an inlined LRVH (Load Reversed Half-word) instruction. The SystemZ back-end did not support this opcode and the inlined assembly would cause a fatal error. Reviewers: bryanpkc, uweigand Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D18732 llvm-svn: 269688
* [WebAssembly] Mark COPY_LOCAL and TEE_LOCAL instructions has having no side ↵Dan Gohman2016-05-161-0/+2
| | | | | | effects. llvm-svn: 269683
* [WebAssembly] Use eqz to negate a branch conditions.Dan Gohman2016-05-161-8/+2
| | | | llvm-svn: 269681
* [WebAssembly] Add a few optimization ideas to README.txt.Dan Gohman2016-05-161-0/+15
| | | | llvm-svn: 269677
* [X86] Remove transformVSELECTtoBlendVECTOR_SHUFFLEMichael Kuperstein2016-05-161-110/+0
| | | | | | | | | | | | | | | The new X86 shuffle lowering can do just fine without transforming vselects into vector_shuffles. It looks like the only thing this code does right now is cause trouble - in particular, it can lead to combine/legalization infinite loops. Note that it's not completely NFC, since some of the shuffle masks get inverted, which may cause slight differences further down the line. We may want to find a way to invert those masks, but that's orthogonal to this commit. This fixes the hang in PR27689. llvm-svn: 269676
* [Hexagon] Make getCallerSavedRegs specific to a register classKrzysztof Parzyszek2016-05-163-33/+61
| | | | llvm-svn: 269674
* [Hexagon] Simplify HexagonInstrInfo::isPredicableKrzysztof Parzyszek2016-05-161-84/+5
| | | | | | | Remove all the checks for constant extenders from isPredicable. The users of it should be the ones checking cost/profitability. llvm-svn: 269664
* Use proper capitalization and punctuation per coding standards. NFC.Chad Rosier2016-05-161-1/+1
| | | | llvm-svn: 269652
* Fixed unused variable warningSimon Pilgrim2016-05-161-1/+0
| | | | llvm-svn: 269650
* [X86][SSSE3] Lower vector CTLZ with PSHUFB lookupsSimon Pilgrim2016-05-161-5/+119
| | | | | | | | | | This patch uses PSHUFB to lower vector CTLZ and avoid (slower) scalarizations. The leading zero count of each 4-bit nibble of the vector is determined by using a PSHUFB lookup. Pairs of results are then repeatedly combined up to the original element width. Differential Revision: http://reviews.llvm.org/D20016 llvm-svn: 269646
* [Sparc][LEON] Add LEON-specific CASA instruction.Chris Dewhurst2016-05-167-22/+69
| | | | | | Differental Revision: http://reviews.llvm.org/D20098 llvm-svn: 269644
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