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* Add BLSI, BLSMSK, and BLSR to getTargetNodeName.Craig Topper2011-11-131-2/+6
| | | | llvm-svn: 144502
* The order in which the predicate is added differs between Thumb and ARM ↵Chad Rosier2011-11-131-10/+16
| | | | | | mode. Fix predicate when in ARM mode and restore SelectIntrinsicCall. llvm-svn: 144494
* Temporarily disable SelectIntrinsicCall when in ARM mode. This is causing ↵Chad Rosier2011-11-131-0/+1
| | | | | | failures. llvm-svn: 144492
* Fix comments.Chad Rosier2011-11-131-3/+3
| | | | llvm-svn: 144490
* Add support for emitting both signed- and zero-extend loads. Fix Chad Rosier2011-11-131-32/+91
| | | | | | | | | | | | | SimplifyAddress to handle either a 12-bit unsigned offset or the ARM +/-imm8 offsets (addressing mode 3). This enables a load followed by an integer extend to be folded into a single load. For example: ldrb r1, [r0] ldrb r1, [r0] uxtb r2, r1 => mov r3, r2 mov r3, r1 llvm-svn: 144488
* Add more AVX2 shift lowering support. Move AVX2 variable shift to use ↵Craig Topper2011-11-122-62/+153
| | | | | | patterns instead of custom lowering code. llvm-svn: 144457
* Fix typo.Akira Hatanaka2011-11-121-1/+1
| | | | llvm-svn: 144453
* Implement Mips64's handling of byval arguments in LowerCall.Akira Hatanaka2011-11-121-12/+100
| | | | llvm-svn: 144452
* Implement Mips64's handling of byval arguments in LowerFormalArguments.Akira Hatanaka2011-11-121-18/+60
| | | | llvm-svn: 144449
* 64-bit arbitrary immediate pattern.Akira Hatanaka2011-11-121-0/+4
| | | | llvm-svn: 144448
* Function for handling byval arguments.Akira Hatanaka2011-11-122-4/+43
| | | | llvm-svn: 144447
* build: Attempt to rectify inconsistencies between CMake and LLVMBuild ↵Daniel Dunbar2011-11-1225-21/+25
| | | | | | | | versions of explicit dependencies. - The hope is that we have a tool/test to verify these are accurate (and tight) soon. llvm-svn: 144444
* ARM refactor simple immediate asm operand render methods.Jim Grosbach2011-11-124-79/+22
| | | | | | | These immediate operands all use the same simple logic for rendering to MCInst, so have them share the method for doing so. llvm-svn: 144439
* Re-apply 144430, this time with the associated isel and disassmbler bits.Jim Grosbach2011-11-123-11/+6
| | | | | | Original commit msg: 'ARM assembly parsing for VST1 two-register encoding.' llvm-svn: 144437
* Oops. Missed the isel half of this. revert while I sort that out.Jim Grosbach2011-11-111-3/+4
| | | | llvm-svn: 144431
* ARM assembly parsing for VST1 two-register encoding.Jim Grosbach2011-11-111-4/+3
| | | | llvm-svn: 144430
* ARM optional size suffix for VLDR/VSTR syntax.Jim Grosbach2011-11-111-0/+9
| | | | llvm-svn: 144427
* Add support in fast-isel for selecting memset/memcpy/memmove intrinsics.Chad Rosier2011-11-111-10/+60
| | | | llvm-svn: 144426
* CMake: Fix CMake build for new Mips tblgen file.Daniel Dunbar2011-11-111-0/+1
| | | | llvm-svn: 144423
* ARM vldm and vstm VFP instructions can take a data type suffix.Jim Grosbach2011-11-111-0/+22
| | | | | | | | | | | | It's ignored by the assembler when present, but is legal syntax. Other instructions have something similar, but for some mnemonics it's only sometimes not significant, so this quick check in the parser will need refactored into something more robust soon-ish. This gets some basics working in the meantime. Partial for rdar://10435264 llvm-svn: 144422
* Target/LLVMBuild: Order components alphabetically.Daniel Dunbar2011-11-111-16/+16
| | | | llvm-svn: 144415
* Mips MC object code emission improvements:Bruno Cardoso Lopes2011-11-1113-130/+475
| | | | | | | | | | "With this patch we can now generate runnable Mips code through LLVM direct object emission. We have run numerous simple programs, both C and C++ and with -O0 and -O3 from the output. The code is not production ready, but quite useful for experimentation." Patch and message by Jack Carter llvm-svn: 144414
* Nuke no longer accurate comment.Jim Grosbach2011-11-111-3/+0
| | | | llvm-svn: 144411
* Preserve MachineMemOperands in ARMLoadStoreOptimizer.Andrew Trick2011-11-111-0/+22
| | | | | | Fixes PR8113. llvm-svn: 144409
* ARM allow Q registers in vldm/vstm register lists.Jim Grosbach2011-11-111-27/+45
| | | | | | rdar://9672822 llvm-svn: 144407
* allow non-device function calls in PTX when natively handling device-side printfDan Bailey2011-11-114-23/+129
| | | | llvm-svn: 144388
* add rules in tabgen for PTX COPY_ADDRESS of frameindexDan Bailey2011-11-111-0/+6
| | | | llvm-svn: 144387
* Remove the unnecessary dependency on libARMCodeGen from libARMDisassembler.Benjamin Kramer2011-11-111-1/+1
| | | | llvm-svn: 144384
* Remove the unnecessary dependency on libMBlazeCodeGen from ↵Benjamin Kramer2011-11-112-9/+2
| | | | | | libMBlazeDisassembler. llvm-svn: 144383
* Add lowering for AVX2 shift instructions.Craig Topper2011-11-112-117/+167
| | | | llvm-svn: 144380
* Rename variables to avoid confusion. No functionallity change intended.Chad Rosier2011-11-111-18/+18
| | | | llvm-svn: 144377
* Add support for using immediates with select instructions.Chad Rosier2011-11-111-8/+40
| | | | | | rdar://10412592 llvm-svn: 144376
* Do not try to detect DAG combine patterns for integer multiply-add/sub if valueAkira Hatanaka2011-11-111-2/+4
| | | | | | | type is not i32. MIPS does not have 64-bit integer multiply-add/sub instructions. llvm-svn: 144373
* 64-bit atomic instructions.Akira Hatanaka2011-11-113-64/+194
| | | | llvm-svn: 144372
* Modify LowerFRAMEADDR. Use 64-bit register FP_64 when ABI is N64.Akira Hatanaka2011-11-111-1/+2
| | | | llvm-svn: 144371
* Add 64-bit versions of LEA_ADDiu and DynAlloc. Modify LowerDYNAMIC_STACKALLOC.Akira Hatanaka2011-11-113-12/+27
| | | | llvm-svn: 144370
* 64-bit versions of jal, jalr and bal.Akira Hatanaka2011-11-112-0/+27
| | | | llvm-svn: 144368
* Emit Mips64's sequence of instructions that set global register in prologue.Akira Hatanaka2011-11-111-1/+21
| | | | llvm-svn: 144367
* Fix printing of MCSymbolRegExpr. Needs three closing parentheses forAkira Hatanaka2011-11-111-1/+4
| | | | | | VK_Mips_GPOFF_HI/LO. llvm-svn: 144366
* Make sure to expand SIGN_EXTEND_INREG for NEON vectors. PR11319, round 3.Eli Friedman2011-11-111-0/+1
| | | | llvm-svn: 144361
* When loading a value, treat an i1 as an i8.Chad Rosier2011-11-111-0/+1
| | | | llvm-svn: 144356
* If we have to reset the calculation of the compact encoding, then also reset theBill Wendling2011-11-111-0/+1
| | | | | | | "saved register" index. <rdar://problem/10430076> llvm-svn: 144350
* Add support for using MVN to materialize negative constants.Chad Rosier2011-11-111-3/+17
| | | | | | rdar://10412592 llvm-svn: 144348
* LLVMBuild: Add explicit information on whether targets define an assembly ↵Daniel Dunbar2011-11-1110-0/+16
| | | | | | printer, assembly parser, or disassembler. llvm-svn: 144344
* Thumb2 ldm/stm updating w/ one register in the list are LDR/STR.Jim Grosbach2011-11-101-0/+32
| | | | | | rdar://10429490 llvm-svn: 144338
* ARM let processInstruction() tranforms chain.Jim Grosbach2011-11-101-15/+37
| | | | llvm-svn: 144337
* Thumb2 parsing for push/pop w/ hi registers in the reglist.Jim Grosbach2011-11-101-2/+32
| | | | | | rdar://10130228. llvm-svn: 144331
* Thumb1 diagnostics for reglist on PUSH/POP fix.Jim Grosbach2011-11-101-2/+2
| | | | | | Was not checking the first register in the register list. llvm-svn: 144329
* Thumb MUL assembly parsing for 3-operand form.Jim Grosbach2011-11-101-7/+9
| | | | | | | | | Get the source register that isn't tied to the destination register correct, even when the assembly source operand order is backwards. rdar://10428630 llvm-svn: 144322
* build/MBlazeDisassembler: Some compilers may generate an MBlaze disassemblerDaniel Dunbar2011-11-101-1/+7
| | | | | | | that depends on MBlazeCodeGen. This is a layering violation that should really be fixed. llvm-svn: 144321
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