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* When in ARM mode, LDRH/STRH require special handling of negative offsets.Chad Rosier2011-11-101-1/+2
| | | | | | | For correctness, disable this for now. rdar://10418009 llvm-svn: 144316
* ARM .thumb_func directive for quoted symbol names.Jim Grosbach2011-11-101-3/+3
| | | | | | | | | Use the getIdentifier() method of the token, not getString(), otherwise we keep the quotes as part of the symbol name, which we don't want. rdar://10428015 llvm-svn: 144315
* ARM assembly parsing for LSR/LSL/ROR(immediate).Jim Grosbach2011-11-102-6/+50
| | | | | | More of rdar://9704684 llvm-svn: 144301
* ARM assembly parsing for ASR(immediate).Jim Grosbach2011-11-103-7/+37
| | | | | | Start of rdar://9704684 llvm-svn: 144293
* build: Rename CBackend and CppBackend libraries to have CodeGen suffix, forDaniel Dunbar2011-11-104-6/+6
| | | | | | consistency with other targets. llvm-svn: 144292
* AVX2: Add variable shift from memory.Nadav Rotem2011-11-101-1/+24
| | | | | | | | Note: These patterns only works in some cases because many times the load sd node is bitcasted from a load node of a different type. llvm-svn: 144266
* For immediate encodings of icmp, zero or sign extend first. ThenChad Rosier2011-11-101-5/+5
| | | | | | | determine if the value is negative and flip the sign accordingly. rdar://10422026 llvm-svn: 144258
* build/Make & CMake: Pass the appropriate --native-target and --enable-targetsDaniel Dunbar2011-11-101-2/+3
| | | | | | options to llvm-build, so the all-targets etc. components are defined properly. llvm-svn: 144255
* llvm-build: Add --native-target and --enable-targets options, and add logic toDaniel Dunbar2011-11-1013-16/+16
| | | | | | | | | | handle defining the "magic" target related components (like native, nativecodegen, and engine). - We still require these components to be in the project (currently in lib/Target) so that we have a place to document them and hopefully make it more obvious that they are "magic". llvm-svn: 144253
* llvm-build: Change CBackend and CppBackend to not use library_name. This willDaniel Dunbar2011-11-102-2/+0
| | | | | | | | | change the generated library .a file name once we fully switch over, but simplifies how we treat these targets without requiring more special casing (since their library group name and the codegen library name currently map to the same "llvm-config" style component name). llvm-svn: 144251
* llvm-build: Add an explicit component type to represent targets.Daniel Dunbar2011-11-1012-12/+16
| | | | | | - Gives us a place to hang target specific metadata (like whether the target has a JIT). llvm-svn: 144250
* Tidy up.Jim Grosbach2011-11-101-12/+0
| | | | llvm-svn: 144244
* Thumb2 assembly parsing STMDB w/ optional .w suffix.Jim Grosbach2011-11-091-0/+6
| | | | | | rdar://10422955 llvm-svn: 144242
* Make sure we correctly unroll conversions between v2f64 and v2i32 on ARM.Eli Friedman2011-11-091-1/+25
| | | | llvm-svn: 144241
* The ARM LDRH/STRH instructions use a +/-imm8 encoding, not an imm12.Chad Rosier2011-11-091-5/+13
| | | | | | rdar://10418009 llvm-svn: 144213
* AVX2: Add patterns for variable shift operationsNadav Rotem2011-11-092-0/+40
| | | | llvm-svn: 144212
* Remove unnecessary include.Devang Patel2011-11-092-2/+0
| | | | llvm-svn: 144211
* Add AVX2 support for vselect of v32i8Nadav Rotem2011-11-092-0/+8
| | | | llvm-svn: 144187
* Enable execution dependency fix pass for YMM registers when AVX2 is enabled. ↵Craig Topper2011-11-092-4/+20
| | | | | | Add AVX2 logical operations to list of replaceable instructions. llvm-svn: 144179
* Add instruction selection for AVX2 integer comparisons.Craig Topper2011-11-092-8/+43
| | | | llvm-svn: 144176
* Add AVX2 instruction lowering for add, sub, and mul.Craig Topper2011-11-091-24/+81
| | | | llvm-svn: 144174
* Add support for encoding immediates in icmp and fcmp. Hopefully, this willChad Rosier2011-11-091-12/+64
| | | | | | | remove a fair number of unnecessary materialized constants. rdar://10412592 llvm-svn: 144163
* Hide cpu name checking in ARMSubtarget.Evan Cheng2011-11-092-1/+2
| | | | llvm-svn: 144154
* Properly handle Mips MC relocations and lower cpload and cprestore macros to ↵Bruno Cardoso Lopes2011-11-084-45/+191
| | | | | | | | MCInsts. Patch by Jack Carter. llvm-svn: 144139
* Add workaround for Cortex-M3 errata 602117 by replacing ldrd x, y, [x] with ↵Evan Cheng2011-11-081-3/+9
| | | | | | ldm or ldr pairs. llvm-svn: 144123
* ARMFastISel doesn't support thumb1. Rename isThumb to isThumb2 to reflect this.Chad Rosier2011-11-081-39/+39
| | | | | | No functional change intended. llvm-svn: 144122
* Lower mem-ops to unaligned i32/i16 load/stores on ARM where supported.Lang Hames2011-11-081-0/+7
| | | | | | | | Add support for trimming constants to GetDemandedBits. This fixes some funky constant generation that occurs when stores are expanded for targets that don't support unaligned stores natively. llvm-svn: 144102
* Added invariant field to the DAG.getLoad method and changed all calls.Pete Cooper2011-11-0812-130/+155
| | | | | | When this field is true it means that the load is from constant (runt-time or compile-time) and so can be hoisted from loops or moved around other memory accesses llvm-svn: 144100
* This patch handles unaligned loads and stores in Mips JIT. Mips backendBruno Cardoso Lopes2011-11-082-6/+148
| | | | | | | | | | | | implements unaligned loads and stores with assembler macro-instructions ulw, usw, ulh, ulhu, ush, and this patch emits corresponding instructions instead of these macros. Since each unaligned load/store is expanded into two corresponding loads/stores where offset for second load/store is modified by +3 (for words) or +1 (for halfwords). Patch by Petar Jovanovic and Sasa Stankovic. llvm-svn: 144081
* PPCInstrInfo.cpp: Fix one "unused" warning.NAKAMURA Takumi2011-11-081-0/+1
| | | | llvm-svn: 144071
* Make sure to mark vector extload's as expand on ARM. Fixes PR11319.Eli Friedman2011-11-081-9/+11
| | | | llvm-svn: 144057
* Add x86 isel logic and patterns to match movlps from clang generated IR for ↵Evan Cheng2011-11-082-6/+11
| | | | | | _mm_loadl_pi(). rdar://10134392, rdar://10050222 llvm-svn: 144052
* Enable support for returning i1, i8, and i16. Nothing special todo as it's theChad Rosier2011-11-082-1/+9
| | | | | | | | callee's responsibility to sign or zero-extend the return value. The additional test case just checks to make sure the calls are selected (i.e., -fast-isel-abort doesn't assert). llvm-svn: 144047
* Allow i1 to be promoted to i32 for ARM AAPCS and AAPCS-VFP calling ↵Chad Rosier2011-11-071-1/+1
| | | | | | convention as well. llvm-svn: 144021
* Various Mips64 floating point instruction patterns.Akira Hatanaka2011-11-071-3/+18
| | | | llvm-svn: 144019
* Add definition of the base class for floating point comparison instructionsAkira Hatanaka2011-11-071-8/+8
| | | | | | and add Mips64's version too. llvm-svn: 144018
* Add code needed for copying between 64-bit integer and floating pointerAkira Hatanaka2011-11-071-0/+6
| | | | | | registers. llvm-svn: 144017
* Add definitions of 64-bit instructions which move data between integer andAkira Hatanaka2011-11-071-0/+8
| | | | | | floating pointer registers. llvm-svn: 144016
* Simplify some uses of utohexstr.Benjamin Kramer2011-11-072-4/+3
| | | | | | As a side effect hex is printed lowercase instead of uppercase now. llvm-svn: 144013
* Simplify code. No functionality change.Benjamin Kramer2011-11-071-155/+91
| | | | llvm-svn: 144012
* Expand V_SET0 to xorps by default.Jakob Stoklund Olesen2011-11-071-1/+1
| | | | | | | | | The xorps instruction is smaller than pxor, so prefer that encoding. The ExecutionDepsFix pass will switch the encoding to pxor and xorpd when appropriate. llvm-svn: 143996
* Add definition of 64-bit load upper immediate.Akira Hatanaka2011-11-072-3/+4
| | | | llvm-svn: 143994
* Include RegSaveAreaSize in the computation of stack size.Akira Hatanaka2011-11-071-0/+1
| | | | llvm-svn: 143993
* Define functions that get or set the size of area on callee's stack frame whichAkira Hatanaka2011-11-071-1/+10
| | | | | | is used to save va_arg or byval arguments passed in registers. llvm-svn: 143992
* Use array_lengthof to compute the number of iterations of a loop.Akira Hatanaka2011-11-071-6/+6
| | | | llvm-svn: 143991
* Fix patterns for unaligned 32-bit load. DSLL32 or DSRL32 should be emittedAkira Hatanaka2011-11-071-2/+2
| | | | | | when shift amount is larger than 32. llvm-svn: 143990
* Make the type of shift amount i32 in order to reduce the number of shiftAkira Hatanaka2011-11-073-5/+7
| | | | | | instruction definitions. llvm-svn: 143989
* Add 64-bit to 32-bit trunc pattern.Akira Hatanaka2011-11-071-0/+5
| | | | llvm-svn: 143988
* Add AVX2 variable shift instructions and intrinsics.Craig Topper2011-11-071-0/+40
| | | | llvm-svn: 143915
* Add AVX2 VPMOVMASK instructions and intrinsics.Craig Topper2011-11-071-0/+38
| | | | llvm-svn: 143904
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