summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* Revert r143206, as there are still some failing tests.Dan Gohman2011-10-294-212/+14
| | | | llvm-svn: 143262
* ARM mode 'mov' to 'mvn' assembler alias.Jim Grosbach2011-10-282-2/+30
| | | | llvm-svn: 143237
* Add Thumb2 alias for "mov Rd, #imm" to "mvn Rd, #~imm".Jim Grosbach2011-10-282-1/+29
| | | | | | | | | | | When '~imm' is encodable as a t2_so_imm but plain 'imm' is not. For example, mov r2, #-3 becomes mvn r2, #2 rdar://10349224 llvm-svn: 143235
* Specify that the high bit of the alignment field is fixed to 0 on these ↵Owen Anderson2011-10-281-2/+2
| | | | | | instructions. llvm-svn: 143220
* Make changes necessary in LowerFormalArguments to support Mips64.Akira Hatanaka2011-10-281-17/+17
| | | | llvm-svn: 143218
* Make changes necessary in LowerCall to support Mips64.Akira Hatanaka2011-10-281-25/+38
| | | | llvm-svn: 143217
* Add variable IsO32 to MipsTargetLowering.Akira Hatanaka2011-10-282-10/+11
| | | | llvm-svn: 143213
* Reapply r143202, with a manual decoding hook for SWP. This change ↵Owen Anderson2011-10-283-1/+27
| | | | | | inadvertantly exposed a decoding ambiguity between SWP and CPS that the auto-generated decoder can't handle. llvm-svn: 143208
* Reapply r143177 and r143179 (reverting r143188), with schedulerDan Gohman2011-10-284-14/+212
| | | | | | | | | fixes: Use a separate register, instead of SP, as the calling-convention resource, to avoid spurious conflicts with actual uses of SP. Also, fix unscheduling of calling sequences, which can be triggered by pseudo-two-address dependencies. llvm-svn: 143206
* Revert r143202.Owen Anderson2011-10-281-1/+1
| | | | llvm-svn: 143203
* Specify fixed bits on CPS instructions to enable roundtripping.Owen Anderson2011-10-281-1/+1
| | | | llvm-svn: 143202
* Thumb2 ADD/SUB instructions encoding selection outside IT block.Jim Grosbach2011-10-281-0/+21
| | | | | | | | | | | Outside an IT block, "add r3, #2" should select a 32-bit wide encoding rather than generating an error indicating the 16-bit encoding is only legal in an IT block (outside, the 'S' suffic is required for the 16-bit encoding). rdar://10348481 llvm-svn: 143201
* Speculatively disable Dan's commits 143177 and 143179 to see ifDuncan Sands2011-10-284-212/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | it fixes the dragonegg self-host (it looks like gcc is miscompiled). Original commit messages: Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUW on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. Delete #if 0 code accidentally left in. llvm-svn: 143188
* Eliminate LegalizeOps' LegalizedNodes map and have it just call RAUWDan Gohman2011-10-284-14/+212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | on every node as it legalizes them. This makes it easier to use hasOneUse() heuristics, since unneeded nodes can be removed from the DAG earlier. Make LegalizeOps visit the DAG in an operands-last order. It previously used operands-first, because LegalizeTypes has to go operands-first, and LegalizeTypes used to be part of LegalizeOps, but they're now split. The operands-last order is more natural for several legalization tasks. For example, it allows lowering code for nodes with floating-point or vector constants to see those constants directly instead of seeing the lowered form (often constant-pool loads). This makes some things somewhat more complicated today, though it ought to allow things to be simpler in the future. It also fixes some bugs exposed by Legalizing using RAUW aggressively. Remove the part of LegalizeOps that attempted to patch up invalid chain operands on libcalls generated by LegalizeTypes, since it doesn't work with the new LegalizeOps traversal order. Instead, define what LegalizeTypes is doing to be correct, and transfer the responsibility of keeping calls from having overlapping calling sequences into the scheduler. Teach the scheduler to model callseq_begin/end pairs as having a physical register definition/use to prevent calls from having overlapping calling sequences. This is also somewhat complicated, though there are ways it might be simplified in the future. This addresses rdar://9816668, rdar://10043614, rdar://8434668, and others. Please direct high-level questions about this patch to management. llvm-svn: 143177
* ARM Allow 'q' registers in VLD/VST vector lists.Jim Grosbach2011-10-281-4/+47
| | | | | | | | Just treat it as if the constituent D registers where specified. rdar://10348896 llvm-svn: 143167
* Remove the Alpha backend.Dan Gohman2011-10-2739-5315/+0
| | | | llvm-svn: 143164
* Add some NEON stores to the VLD decoding hook that were accidentally omitted ↵Owen Anderson2011-10-271-0/+4
| | | | | | previously. llvm-svn: 143162
* Also set addrmode6 alignment when align==size.Jakob Stoklund Olesen2011-10-271-1/+1
| | | | | | | Previously, we were only setting the alignment bits on over-aligned loads and stores. llvm-svn: 143160
* ARM isel for vld1, opcode selection for register stride post-index pseudos.Jim Grosbach2011-10-271-0/+4
| | | | llvm-svn: 143158
* Avoid partial CPSR dependency from loop backedges. rdar://10357570Evan Cheng2011-10-271-24/+43
| | | | llvm-svn: 143145
* Change the sysexit mnemonic (and sysexitl) to never have the REX.W prefix andKevin Enderby2011-10-272-3/+3
| | | | | | | not depend on In32BitMode. Use the sysexitq mnemonic for the version with the REX.W prefix and only allow it only In64BitMode. rdar://9738584 llvm-svn: 143112
* Thumb2 t2LDMDB[_UPD] assembly parsing to recognize .w suffix.Jim Grosbach2011-10-271-0/+6
| | | | | | rdar://10348844 llvm-svn: 143110
* Thumb2 t2MVNi assembly parsing to recognize ".w" suffix.Jim Grosbach2011-10-271-1/+3
| | | | | | rdar://10348584 llvm-svn: 143108
* A branch predicated on a constant can just FastEmit an unconditional branch.Chad Rosier2011-10-271-0/+6
| | | | llvm-svn: 143086
* Rename NonScalarIntSafe to something more appropriate.Lang Hames2011-10-264-9/+9
| | | | llvm-svn: 143080
* Add a TODO comment. FastISel works by parsing each basic block from the bottomChad Rosier2011-10-261-0/+1
| | | | | | | | up. Thus, improving the support for compares is goodness because it increases the number of terminator instructions we can handle. This creates many more opportunities for target specific fast-isel. llvm-svn: 143079
* Factor a little more code into EmitCmp, which should have been done in the firstChad Rosier2011-10-261-23/+16
| | | | | | place. No functional change intended. llvm-svn: 143078
* Use EmitCmp in SelectBranch. No functional change intended.Chad Rosier2011-10-261-33/+6
| | | | llvm-svn: 143076
* Factor out an EmitCmp function that can be used by both SelectCmp andChad Rosier2011-10-261-18/+24
| | | | | | SelectBranch. No functional change intended. llvm-svn: 143072
* Thumb2 ldr pc-relative encoding fixes.Jim Grosbach2011-10-262-7/+16
| | | | | | | | | We were parsing label references to the i12 encoding, which isn't right. They need to go to the pci variant instead. More of rdar://10348687 llvm-svn: 143068
* Fixes an issue reported by -verify-machineinstrs.Rafael Espindola2011-10-262-6/+7
| | | | | | Patch by Sanjoy Das. llvm-svn: 143064
* ARM parse parenthesized expressions for label references.Jim Grosbach2011-10-261-0/+1
| | | | | | Partial fix for rdar://10348687. llvm-svn: 143063
* This commit introduces two fake instructions MORESTACK_RET andRafael Espindola2011-10-263-21/+39
| | | | | | | | | | | | MORESTACK_RET_RESTORE_R10; which are lowered to a RET and a RET followed by a MOV respectively. Having a fake instruction prevents the verifier from seeing a MachineBasicBlock end with a non-terminator (MOV). It also prevents the rather eccentric case of a MachineBasicBlock ending with RET but having successors nevertheless. Patch by Sanjoy Das. llvm-svn: 143062
* Make sure short memsets on ARM lower to stores, even when optimizing for size.Lang Hames2011-10-261-0/+2
| | | | llvm-svn: 143055
* Thumb2 remove redundant ".w" suffix from t2MVNCCi pattern.Jim Grosbach2011-10-261-1/+1
| | | | llvm-svn: 143034
* Revert r142530 at least temporarily while a discussion is had on ↵James Molloy2011-10-261-5/+2
| | | | | | llvm-commits regarding exactly how much optsize should optimize for size over performance. llvm-svn: 143023
* Use a worklist to prevent the iterator from becoming invalidated because of ↵Bill Wendling2011-10-261-3/+4
| | | | | | the 'removeSuccessor' call. Noticed in a Release+Asserts+Check buildbot. llvm-svn: 143018
* Revert part of r142530. The patch potentially hurts performance especiallyEvan Cheng2011-10-261-3/+3
| | | | | | | on Darwin platforms where -Os means optimize for size without hurting performance. llvm-svn: 143002
* Corrects previously incorrect $sp change in MipsCompilationCallback.Bruno Cardoso Lopes2011-10-251-7/+7
| | | | | | | | The address for $sp, and addresses for sdc1/ldc1 must be 8-byte aligned Patch by Petar Jovanovic. llvm-svn: 142930
* ARM assembly parsing and encoding for VLD1 with writeback.Jim Grosbach2011-10-253-17/+33
| | | | | | Four entry register lists. llvm-svn: 142882
* Remove the Blackfin backend.Dan Gohman2011-10-2537-4415/+0
| | | | llvm-svn: 142880
* Remove the SystemZ backend.Dan Gohman2011-10-2437-6279/+0
| | | | llvm-svn: 142878
* Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.Jim Grosbach2011-10-243-4/+0
| | | | llvm-svn: 142877
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-244-21/+33
| | | | | | Three entry register list variation. llvm-svn: 142876
* Don't crash on variable insertelement on ARM. PR10258.Eli Friedman2011-10-241-0/+11
| | | | llvm-svn: 142871
* ARMConstantPoolMBB::print should print BB number.Evan Cheng2011-10-241-0/+1
| | | | llvm-svn: 142867
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-242-0/+38
| | | | | | One and two length register list variants. llvm-svn: 142861
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-245-71/+181
| | | | | | | | Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. llvm-svn: 142853
* Add support to the old JIT for acquire/release loads and stores on x86. ↵Eli Friedman2011-10-241-9/+24
| | | | | | PR11207. llvm-svn: 142841
* Fix a NEON disassembly case that was broken in the recent refactorings. As ↵Owen Anderson2011-10-241-6/+0
| | | | | | more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. llvm-svn: 142817
OpenPOWER on IntegriCloud