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* AMDGPU: Remove abs intrinsicMatt Arsenault2016-01-203-16/+0
| | | | llvm-svn: 258343
* AMDGPU: Remove min/max intrinsicsMatt Arsenault2016-01-202-48/+0
| | | | | | This removes support for mesa 11.0.x llvm-svn: 258342
* Write AArch64 big endian data fixup entries as BE.Keith Walker2016-01-201-35/+64
| | | | | | | | | | | | | | There was support for writing the AArch64 big endian data fixup entries in the .eh_frame section in BE. This is changed to write all such fixup entries in BE with no restriction on the section. This is similar to the existing support for fixup entries for ARM. A test is added to check the length field in the .debug_line section as this is an example of where such a fixup occurs. Differential Revision: http://reviews.llvm.org/D16064 llvm-svn: 258320
* Correctly initialize SIAnnotateControlFlowTom Stellard2016-01-203-2/+11
| | | | | | | | | | Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D16304 llvm-svn: 258319
* [AVX512] Adding VPERMB Intrinsics Michael Zuckerman2016-01-201-0/+3
| | | | | | Differential Revision: http://reviews.llvm.org/D16296 llvm-svn: 258316
* Fixing bug in rL258132: [X86] Adding support for missing variations of X86 ↵Marina Yatsina2016-01-201-2/+6
| | | | | | | | | | string related instructions There was a bug in my rL258132 because there's an overloading of the "movsd" and "cmpsd" instructions, e.g. movsd can be either "Move Data from String to String" (the case I wanted to handle) or "Move or Merge Scalar Double-Precision Floating-Point Value" (the case that causes the asserts). Added code for escaping the unfamiliar scenarios and falling back to old behviour. Also changed the asserts to llvm_unreachable. llvm-svn: 258312
* AVX512: Store (MOVNTPD, MOVNTPS, MOVNTDQ) using non-temporal hint intrinsic ↵Igor Breger2016-01-203-38/+36
| | | | | | | | implementation. Differential Revision: http://reviews.llvm.org/D16350 llvm-svn: 258309
* [AArch64] Fix two bugs in the .inst directiveOliver Stannard2016-01-201-1/+13
| | | | | | | | | | | | | | The AArch64 .inst directive was implemented using EmitIntValue, which resulted in both $x and $d (code and data) mapping symbols being emitted at the same address. This fixes it to only emit the $x mapping symbol. EmitIntValue also emits the value in big-endian order when targeting big-endian systems, but instructions are always emitted in little-endian order for AArch64. Differential Revision: http://reviews.llvm.org/D16349 llvm-svn: 258308
* [WebAssembly] Minor code cleanups. NFC.Dan Gohman2016-01-206-12/+13
| | | | llvm-svn: 258294
* [WebAssembly] Remove the Relooper code, as it is not currently being used.Dan Gohman2016-01-204-1173/+0
| | | | llvm-svn: 258293
* [WebAssembly] Don't stackify stores across instructions with side effects.Dan Gohman2016-01-201-1/+1
| | | | llvm-svn: 258285
* [NFC] Replace several manual GEP loops with gep_type_iterator.Eduard Burtescu2016-01-201-16/+9
| | | | | | | | | | Reviewers: dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D16335 llvm-svn: 258262
* RegisterPressure: Make liveness tracking subregister awareMatthias Braun2016-01-202-7/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D14968 llvm-svn: 258258
* AMDGPU/SI: Prevent the DAGCombiner from creating setcc with i1 inputsTom Stellard2016-01-202-0/+12
| | | | | | | | | | Reviewers: arsenm Subscribers: arsenm, llvm-commits Differential Revision: http://reviews.llvm.org/D15035 llvm-svn: 258256
* [X86] Do not run shrink-wrapping on function with split-stack attribute or HiPEQuentin Colombet2016-01-191-1/+17
| | | | | | | | | | | calling convention. The implementation of the related callbacks in the x86 backend for such functions are not ready to deal with a prologue block that is not the entry block of the function. This fixes PR26107, but the longer term solution would be to fix those callbacks. llvm-svn: 258221
* [MC, COFF] Add .reloc support for WinCOFFDavid Majnemer2016-01-194-16/+24
| | | | | | | This adds rudimentary support for a few relocations that we will use for the CodeView debug format. llvm-svn: 258216
* [X86][SSE] Add VZEXT_MOVL target shuffle decoding.Simon Pilgrim2016-01-191-0/+5
| | | | | | Add support for decoding VZEXT_MOVL target shuffle masks, allowing it to be used as a source in target shuffle combines. llvm-svn: 258215
* [X86][SSE] Add INSERTPS target shuffle combines.Simon Pilgrim2016-01-191-0/+137
| | | | | | | | | | As vector shuffles can only reference two inputs many (V)INSERTPS patterns end up being split over two targets shuffles. This patch adds combines to attempt to combine (V)INSERTPS nodes with input/output nodes that are just zeroing out these additional vector elements. Differential Revision: http://reviews.llvm.org/D16072 llvm-svn: 258205
* [AArch64] Remove a bunch of useless FIXME comments.Chad Rosier2016-01-191-4/+0
| | | | llvm-svn: 258193
* [WebAssembly] Remove an unused data member. NFC.Dan Gohman2016-01-193-10/+7
| | | | llvm-svn: 258192
* [AArch64] Remove more dead code after r258093.Chad Rosier2016-01-191-12/+4
| | | | llvm-svn: 258191
* WebAssembly: mark known failure caused by r258125JF Bastien2016-01-191-0/+3
| | | | | | | The following test program triggers the assertion: https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.c-torture/execute/20030916-1.c llvm-svn: 258182
* [AVX512] Adding VPERMT2B and VPERMI2B instruction .Michael Zuckerman2016-01-191-12/+22
| | | | | | Differential Revision: http://reviews.llvm.org/D16297 llvm-svn: 258161
* [opaque pointer types] [NFC] GEP: replace get(Pointer)ElementType uses with ↵Eduard Burtescu2016-01-191-1/+7
| | | | | | | | | | | | | | | | | | get{Source,Result}ElementType. Summary: GEPOperator: provide getResultElementType alongside getSourceElementType. This is made possible by adding a result element type field to GetElementPtrConstantExpr, which GetElementPtrInst already has. GEP: replace get(Pointer)ElementType uses with get{Source,Result}ElementType. Reviewers: mjacob, dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D16275 llvm-svn: 258145
* [AVX512] Adding VPERMB instructionMichael Zuckerman2016-01-192-2/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D16294 llvm-svn: 258144
* [WebAssembly] Rematerialize constants rather than hold them live in registers.Dan Gohman2016-01-194-40/+77
| | | | | | | | | Teach the register stackifier to rematerialize constants that have multiple uses instead of leaving them in registers. In the WebAssembly encoding, it's the same code size to materialize most constants as it is to read a value from a register. llvm-svn: 258142
* Typo.Chad Rosier2016-01-191-1/+1
| | | | llvm-svn: 258137
* [X86] Add support for "xlat m8"Marina Yatsina2016-01-191-0/+11
| | | | | | | | According to x86 spec "xlat m8" is a legal instruction and it is equivalent to "xlatb". Differential Revision: http://reviews.llvm.org/D15150 llvm-svn: 258135
* [X86] Adding support for missing variations of X86 string related instructionsMarina Yatsina2016-01-192-75/+203
| | | | | | | | | | | | | | | The following are legal according to X86 spec: ins mem, DX outs DX, mem lods mem stos mem scas mem cmps mem, mem movs mem, mem Differential Revision: http://reviews.llvm.org/D14827 llvm-svn: 258132
* [WebAssembly] Disable some WebAssembly-specific optimization passes at -O0.Dan Gohman2016-01-191-3/+6
| | | | llvm-svn: 258127
* [WebAssembly] Use the templated form of MachineFunction::getSubtarget(). NFC.Dan Gohman2016-01-192-5/+4
| | | | llvm-svn: 258126
* [X86][AVX512]fix dag & add intrinsics for fixupimmAsaf Badouh2016-01-195-17/+179
| | | | | | | | cover all width and types (pd/ps/sd/ss) of fixupimm instruction and inrtinsics Differential Revision: http://reviews.llvm.org/D16313 llvm-svn: 258124
* AMDGPU: Reduce 64-bit SRAsMatt Arsenault2016-01-182-0/+62
| | | | llvm-svn: 258096
* AMDGPU: Split 64-bit and of constant upMatt Arsenault2016-01-183-2/+70
| | | | | | | | | | This breaks the tests that were meant for testing 64-bit inline immediates, so move those to shl where they won't be broken up. This should be repeated for the other related bit ops. llvm-svn: 258095
* [AArch64] Remove unused arguments. NFC.Chad Rosier2016-01-181-7/+7
| | | | | | AFAICT, these have been unused since the initial backend import. llvm-svn: 258093
* AMDGPU: Generalize shl combineMatt Arsenault2016-01-181-8/+14
| | | | | | | Reduce 64-bit shl with constant > 32. We already special cased this for the == 32 case, but this also works for any >= 32 constant. llvm-svn: 258092
* AMDGPU: Reduce 64-bit lshr by constant to 32-bitMatt Arsenault2016-01-182-0/+45
| | | | | | 64-bit shifts are very slow on some subtargets. llvm-svn: 258090
* AMDGPU: Add subtarget feature for instruction ratesMatt Arsenault2016-01-184-9/+23
| | | | llvm-svn: 258085
* Fixed MSVC Win64 warning of implicit conversion of 32-bit shift to 64-bits.Simon Pilgrim2016-01-181-1/+1
| | | | llvm-svn: 258084
* [X86][AVX2] Broadcast subvectorsSimon Pilgrim2016-01-181-3/+21
| | | | | | | | AVX2 can only broadcast from the zero'th element of a vector, but if the broadcastable element is the zero'th element of a 128-bit subvector its advantageous to extract the subvector, broadcast from that and avoid the loading of shuffle mask data that would be needed for VPERMPS/VPERMD. The only exception being when the source type is 4f64 or 4i64 which can directly use the immediate shuffle VPERMPD/VPERMQ directly. Differential Revision: http://reviews.llvm.org/D16050 llvm-svn: 258081
* [Hexagon] Recognize more copy-equivalents in RDF optimizationsKrzysztof Parzyszek2016-01-181-14/+59
| | | | llvm-svn: 258076
* [RDF] Improvements to copy propagationKrzysztof Parzyszek2016-01-182-72/+145
| | | | | | | - Allow any instruction to define equality between registers. - Keep the DFG updated. llvm-svn: 258075
* [RDF] Improve compile-time performance of dead code eliminationKrzysztof Parzyszek2016-01-182-12/+42
| | | | llvm-svn: 258074
* [RDF] Allow unlinking ref nodes from data-flow chains onlyKrzysztof Parzyszek2016-01-183-14/+23
| | | | llvm-svn: 258073
* AVX512: Masked store intrinsic implementation.Igor Breger2016-01-183-29/+61
| | | | | | | | Implemented intrinsic for the follow instructions (store) : VMOVDQU8/16/32/64, VMOVDQA32/64, VMOVAPS/PD, VMOVUPS/PD. Differential Revision: http://reviews.llvm.org/D16271 llvm-svn: 258047
* Added Cannonlake processor to X86 TargetElena Demikhovsky2016-01-181-1/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D16289 llvm-svn: 258046
* AVX512 : Change v8i1 bitconvert GR8 pattern, remove unnecessary movzbl ↵Igor Breger2016-01-181-1/+1
| | | | | | | | | | | | | | instruction. code example , previous implementation. movzbl %dil, %eax kmovw %eax, %k0 new code kmovw %edi, %k0 Differential Revision: http://reviews.llvm.org/D16287 llvm-svn: 258045
* [ARM] Operands for PKHTB alias should be swappedOliver Stannard2016-01-182-6/+6
| | | | | | | | | When the shift immediate is zero, PKHTB is an alias for PKHBT, but the order of the input operands needs to be swapped. Differential Revision: http://reviews.llvm.org/D16288 llvm-svn: 258044
* [opaque pointer types] [NFC] CallSite: use getFunctionType() instead of ↵Manuel Jacob2016-01-172-10/+3
| | | | | | | | | | | | | | going through PointerType::getElementType. Patch by Eduard Burtescu. Reviewers: dblaikie, mjacob Subscribers: dsanders, llvm-commits, dblaikie Differential Revision: http://reviews.llvm.org/D16273 llvm-svn: 258023
* [AVX512] adding AVXVBMI feature flagMichael Zuckerman2016-01-174-1/+11
| | | | | | | | | | The feature flag is for VPERMB,VPERMI2B,VPERMT2B and VPMULTISHIFTQB instructions. More about the instruction can be found in: hattps://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Differential Revision: http://reviews.llvm.org/D16190 llvm-svn: 258012
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