| Commit message (Collapse) | Author | Age | Files | Lines |
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llvm-svn: 42316
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llvm-svn: 42313
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llvm-svn: 42312
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both results with a single div or idiv instruction. This uses new X86ISD
nodes for DIV and IDIV which are introduced during the legalize phase
so that the SelectionDAG's CSE can automatically eliminate redundant
computations.
llvm-svn: 42308
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the check to see if the assembler supports .loc from X86TargetLowering
into the superclass TargetLowering.
llvm-svn: 42297
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dependency). These are a bunch of instructions that are duplicated so the x86 backend can support both the old and new schemes at the same time. They will be deleted after
all the kinks are worked out.
llvm-svn: 42285
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llvm-svn: 42283
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llvm-svn: 42282
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have situations where an SSE instruction turns into
multiple blocks, with the live range of an x87
register crossing them. To do this correctly make
sure we examine all blocks when inserting
FP_REG_KILL. PR 1697. (This was exposed by my
fix for PR 1681, but the same thing could happen
mixing x87 long double with SSE.)
llvm-svn: 42281
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instead of ISD::LABEL with a manual .debug_line entry when the assembler
supports .file and .loc directives.
llvm-svn: 42278
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aren't really usable without each other.
llvm-svn: 42274
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Fixed some comments
llvm-svn: 42271
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llvm-svn: 42268
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code that creates the label too.
llvm-svn: 42265
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asm to die with:
ScheduleDAG.cpp:269: failed assertion `false && "Couldn't find the register class"'
instead of:
failed assertion `RegMap->getRegClass(VReg) == RC && "Register class of operand and regclass of use don't agree!"'
yay.
llvm-svn: 42259
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keep f32 in SSE registers and f64 in x87. This
is effectively a new codegen mode.
Change addLegalFPImmediate to permit float and
double variants to do different things.
Adjust callers.
llvm-svn: 42246
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llvm-svn: 42239
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Implement calls to functions with byval arguments on X86
llvm-svn: 42192
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llvm-svn: 42189
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initializer is null.
llvm-svn: 42182
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llvm-svn: 42179
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llvm-svn: 42162
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llvm-svn: 42159
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llvm-svn: 42156
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llvm-svn: 42155
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llvm-svn: 42153
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llvm-svn: 42147
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llvm-svn: 42124
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between two registers in the specific class.
llvm-svn: 42123
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tables so that they are eligible for reload/remat folding. And add
entries for JMP and CALL.
llvm-svn: 42094
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and storeRegToStackSlot. Evan and I concluded this
should never be needed and it appears to be true.
(It if is needed, adjustment would be needed for
long double to work.)
llvm-svn: 42049
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Add a new DenseMapInfo::isEqual method to allow clients to redefine
the equality predicate used when probing the hash table.
llvm-svn: 42042
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llvm-svn: 42037
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can terminate a block with no fall-through.
llvm-svn: 42029
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llvm-svn: 42027
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64-bit) can use test instead of cmp with an immediate.
llvm-svn: 42026
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previously only done for 32-bit and smaller operands.
llvm-svn: 42024
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so only works on x86 target).
llvm-svn: 42019
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match the conditional that turns on exception handling emittion in the asm
printer.
llvm-svn: 42008
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supports it. This solves this error on the Darwin x86-64 platform:
$ cat testcase.ii
struct A {
A();
};
A *bork() {
return new A;
}
$ llvm-g++ -arch x86_64 -c testcase.ii
/var/tmp//cc3U8fd8.s:52:unknown section type: non_lazy_symbol_pointers
/var/tmp//cc3U8fd8.s:52:Rest of line ignored. 1st junk character valued 76 (L).
/var/tmp//cc3U8fd8.s:53:Unknown pseudo-op: .indirect_symbol
/var/tmp//cc3U8fd8.s:53:Rest of line ignored. 1st junk character valued 95 (_).
llvm-svn: 41999
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GCC optimizes away things like ptr < NULL to false. To "fix" this,
have the CBE emit casts of pointers to intptr_t when doing relational
pointer comparisons.
llvm-svn: 41983
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llvm-svn: 41975
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double from some of the many places in the optimizers
it appears, and do something reasonable with x86
long double.
Make APInt::dump() public, remove newline, use it to
dump ConstantSDNode's.
Allow APFloats in FoldingSet.
Expand X86 backend handling of long doubles (conversions
to/from int, mostly).
llvm-svn: 41967
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llvm-svn: 41962
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isRegister, isImmediate, and isMachineBasicBlock, which are equivalent,
and more popular.
llvm-svn: 41958
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llvm-svn: 41953
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llvm-svn: 41947
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1.
[(set GR32:$dst, (add GR32:$src1, GR32:$src2)),
(modify EFLAGS)]
This indicates the source pattern expects the instruction would produce 2 values. The first is the result of the addition. The second is an implicit definition in register EFLAGS.
2.
def : Pat<(parallel (addc GR32:$src1, GR32:$src2), (modify EFLAGS)), ()>
Similar to #1 except this is used for def : Pat patterns.
llvm-svn: 41897
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Next round of x87 long double stuff.
Getting close now, basically works.
llvm-svn: 41875
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llvm-svn: 41873
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