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* [Target/ARM] Only enable OptimizeBarrierPass at -O1 and above.Davide Italiano2015-05-201-1/+4
| | | | | | | | | | Ideally this is going to be and LLVM IR pass (shared, among others with AArch64), but for the time being just enable it if consumers ask us for optimization and not unconditionally. Discussed with Tim Northover on IRC. llvm-svn: 237837
* MC: Remove most remaining uses of MCSymbolData::getSymbol(), NFCDuncan P. N. Exon Smith2015-05-201-7/+5
| | | | | | | Remove most remaining calls to `MCSymbolData::getSymbol()`, instead using the already available `MCSymbol` directly. llvm-svn: 237829
* [X86] Remove unused node after morphing it from shr to and.Benjamin Kramer2015-05-201-0/+1
| | | | | | | | | In some cases it won't get cleaned up properly leading to crashes downstream. PR23353. Based on a patch by Davide Italiano. llvm-svn: 237828
* ARM: Fix comment and make it slightly more readableMatthias Braun2015-05-201-7/+7
| | | | llvm-svn: 237820
* Change Function::getIntrinsicID() to return an Intrinsic::ID. NFC.Pete Cooper2015-05-201-2/+2
| | | | | | | | Now that Intrinsic::ID is a typed enum, we can forward declare it and so return it from this method. This updates all users which were either using an unsigned to store it, or had a now unnecessary cast. llvm-svn: 237810
* MC: Update MCAssembler to use MCSymbol, NFCDuncan P. N. Exon Smith2015-05-202-6/+6
| | | | | | Use `MCSymbol` over `MCSymbolData` where both are needed. llvm-svn: 237803
* MC: Use MCSymbol in MachObjectWriter, NFCDuncan P. N. Exon Smith2015-05-203-43/+38
| | | | | | | Replace uses of `MCSymbolData` with `MCSymbol` where both are needed, so we can remove the backpointer. llvm-svn: 237799
* AVX-512: fixed algorithm of building vectors of i1 elementsElena Demikhovsky2015-05-203-65/+134
| | | | | | | | fixed extract-insert i1 element, load i1, zextload i1 should be with "and $1, %reg" to prevent loading garbage. added a bunch of new tests. llvm-svn: 237793
* Revert r237789 - [mips] The naming convention for private labels is ABI ↵Daniel Sanders2015-05-205-23/+2
| | | | | | | | | dependant. It works, but I've noticed that I missed several callers of createMCAsmInfo() and many don't have a TargetMachine to provide. llvm-svn: 237792
* [mips] The naming convention for private labels is ABI dependant.Daniel Sanders2015-05-205-2/+23
| | | | | | | | | | | | | | | | | Summary: For N32/N64, private labels begin with '.L' but for O32 they begin with '$'. MCAsmInfo now has an initializer function which can be used to provide information from the TargetMachine to control the assembly syntax. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: jfb, sandeep, llvm-commits, rafael Differential Revision: http://reviews.llvm.org/D9821 llvm-svn: 237789
* [mips] [IAS] Factor out .set nomacro warning. NFC.Toma Tabacu2015-05-201-8/+11
| | | | | | | | | | | | Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9772 llvm-svn: 237780
* [X86] Implement the local-exec TLS model for Windows targetsDavid Majnemer2015-05-201-14/+19
| | | | | | | We know that _tls_index is zero for local-exec TLS variables because they are always defined in the executable. llvm-svn: 237772
* [bpf] fix buildAlexei Starovoitov2015-05-201-1/+1
| | | | llvm-svn: 237751
* MC: Take MCSymbol in MachObjectWriter::getSymbolAddress(), NFCDuncan P. N. Exon Smith2015-05-204-30/+26
| | | | | | | Pass through an `MCSymbol` instead of an `MCSymbolData` so we can get rid of the back pointer. llvm-svn: 237750
* MC: Use MCSymbol in MCAsmLayout::getSymbolOffset(), NFCDuncan P. N. Exon Smith2015-05-194-10/+10
| | | | | | | Continue to canonicalize on MCSymbol instead of MCSymbolData when both are needed. llvm-svn: 237749
* MachineInstr: Remove unused parameter.Matthias Braun2015-05-193-4/+3
| | | | llvm-svn: 237726
* Remove unnecessary cast. NFCPete Cooper2015-05-191-1/+1
| | | | llvm-svn: 237722
* [mips][microMIPSr6] Implement NOR, OR, ORI, XOR and XORI instructionsZoran Jovanovic2015-05-192-7/+22
| | | | | | Differential Revision: http://reviews.llvm.org/D8800 llvm-svn: 237697
* [mips][microMIPSr6] Implement AND and ANDI instructionsZoran Jovanovic2015-05-192-3/+10
| | | | | | Differential Revision: http://reviews.llvm.org/D8772 llvm-svn: 237696
* [mips] Correct and improve special-case shuffle instructions.Daniel Sanders2015-05-196-114/+271
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Summary: The documentation writes vectors highest-index first whereas LLVM-IR writes them lowest-index first. As a result, instructions defined in terms of left_half() and right_half() had the halves reversed. In addition to correcting them, they have been improved to allow shuffles that use the same operand twice or in reverse order. For example, ilvev used to accept masks of the form: <0, n, 2, n+2, 4, n+4, ...> but now accepts: <0, 0, 2, 2, 4, 4, ...> <n, n, n+2, n+2, n+4, n+4, ...> <0, n, 2, n+2, 4, n+4, ...> <n, 0, n+2, 2, n+4, 4, ...> One further improvement is that splati.[bhwd] is now the preferred instruction for splat-like operations. The other special shuffles are no longer used for splats. This lead to the discovery that <0, 0, ...> would not cause splati.[hwd] to be selected and this has also been fixed. This fixes the enc-3des test from the test-suite on Mips64r6 with MSA. Reviewers: vkalintiris Reviewed By: vkalintiris Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D9660 llvm-svn: 237689
* [mips][microMIPSr6] Implement DIV, DIVU, MOD and MODU instructionsZoran Jovanovic2015-05-192-5/+18
| | | | | | Differential Revision: http://reviews.llvm.org/D8769 llvm-svn: 237685
* [X86] ABI change for x86-32: pass 3 vector arguments in-register instead of ↵Michael Kuperstein2015-05-191-27/+62
| | | | | | | | | | | | | | | | 4, except on Darwin. This changes the ABI used on 32-bit x86 for passing vector arguments. Historically, clang passes the first 4 vector arguments in-register, and additional vector arguments on the stack, regardless of platform. That is different from the behavior of gcc, icc, and msvc, all of which pass only the first 3 arguments in-register. The 3-register convention is documented, unofficially, in Agner's calling convention guide, and, officially, in the recently released version 1.0 of the i386 psABI. Darwin is kept as is because the OS X ABI Function Call Guide explicitly documents the current (4-register) behavior. This fixes PR21510 Differential revision: http://reviews.llvm.org/D9644 llvm-svn: 237682
* Re-land r237175: [X86] Always return the sret parameter in eax/rax ...Reid Kleckner2015-05-181-21/+15
| | | | | | | | | This reverts commit r237210. Also fix X86/complex-fca.ll to match the code that we used to generate on win32 and now generate everwhere to conform to SysV. llvm-svn: 237639
* [mips][microMIPSr6] Implement LSA instructionJozef Kolek2015-05-183-2/+31
| | | | | | | | This patch implements LSA instruction using mapping. Differential Revision: http://reviews.llvm.org/D8919 llvm-svn: 237634
* Simplify IRBuilder::CreateCall* by using ArrayRef+initializer_list/braced ↵David Blaikie2015-05-189-36/+35
| | | | | | init only llvm-svn: 237624
* AArch64: work around ld64 bug more aggressively.Tim Northover2015-05-181-5/+4
| | | | | | | | | | | | | | | ld64 currently mishandles internal pointer relocations (i.e. ARM64_RELOC_UNSIGNED referred to by section & offset rather than symbol). The existing __cfstring clause was an early discovery and workaround for this, but the problem is wider and we should avoid such relocations wherever possible for now. This code should be reverted to allowing internal relocations as soon as possible. PR23437. llvm-svn: 237621
* MachineInstr: Change return value of getOpcode() to unsigned.Matthias Braun2015-05-1811-37/+37
| | | | | | | | | This was previously returning int. However there are no negative opcode numbers and more importantly this was needlessly different from MCInstrDesc::getOpcode() (which even is the value returned here) and SDValue::getOpcode()/SDNode::getOpcode(). llvm-svn: 237611
* MC: Clean up method names in MCContext.Jim Grosbach2015-05-1843-137/+137
| | | | | | | The naming was a mish-mash of old and new style. Update to be consistent with the new. NFC. llvm-svn: 237594
* ARM: allow jump tables to be placed as constant islands.Tim Northover2015-05-187-170/+312
| | | | | | | | | | | | | | | | | Previously, they were forced to immediately follow the actual branch instruction. This was usually OK (the LEAs actually accessing them got emitted nearby, and weren't usually separated much afterwards). Unfortunately, a sufficiently nasty phi elimination dumps many instructions right before the basic block terminator, and this can increase the range too much. This patch frees them up to be placed as usual by the constant islands pass, and consequently has to slightly modify the form of TBB/TBH tables to refer to a PC-relative label at the final jump. The other jump table formats were already position-independent. rdar://20813304 llvm-svn: 237590
* Sparc: support the "set" synthetic instruction.James Y Knight2015-05-183-2/+74
| | | | | | | | | This pseudo-instruction expands into 'sethi' and 'or' instructions, or, just one of them, if the other isn't necessary for a given value. Differential Revision: http://reviews.llvm.org/D9089 llvm-svn: 237585
* Revert r237579, as it broke windows buildbotsOliver Stannard2015-05-186-611/+18
| | | | llvm-svn: 237583
* Sparc: Support PSR, TBR, WIM read/write instructions.James Y Knight2015-05-183-8/+87
| | | | | | Differential Revision: http://reviews.llvm.org/D8971 llvm-svn: 237582
* Sparc: Add the "alternate address space" load/store instructions.James Y Knight2015-05-185-15/+69
| | | | | | | | | | | | | | | | | | - Adds support for the asm syntax, which has an immediate integer "ASI" (address space identifier) appearing after an address, before a comma. - Adds the various-width load, store, and swap in alternate address space instructions. (ldsba, ldsha, lduba, lduha, lda, stba, stha, sta, swapa) This does not attempt to hook these instructions up to pointer address spaces in LLVM, although that would probably be a reasonable thing to do in the future. Differential Revision: http://reviews.llvm.org/D8904 llvm-svn: 237581
* Add support for the Sparc implementation-defined "ASR" registers.James Y Knight2015-05-185-20/+92
| | | | | | | | | | (Note that register "Y" is essentially just ASR0). Also added some test cases for divide and multiply, which had none before. Differential Revision: http://reviews.llvm.org/D8670 llvm-svn: 237580
* [LLVM - ARM/AArch64] Add ACLE special register intrinsicsOliver Stannard2015-05-186-18/+611
| | | | | | | | | | | | | | | | | | | This patch implements LLVM support for the ACLE special register intrinsics in section 10.1, __arm_{w,r}sr{,p,64}. This patch is intended to lower the read/write_register instrinsics, used to implement the special register intrinsics in the clang patch for special register intrinsics (see http://reviews.llvm.org/D9697), to ARM specific instructions MRC,MCR,MSR etc. to allow reading an writing of coprocessor registers in AArch32 and AArch64. This is done by inspecting the register string passed to the intrinsic and then lowering to the appropriate instruction. Patch by Luke Cheeseman. Differential Revision: http://reviews.llvm.org/D9699 llvm-svn: 237579
* [mips][microMIPSr6] Implement ALIGN and AUI instructionsJozef Kolek2015-05-183-4/+59
| | | | | | | | This patch implements ALIGN and AUI instructions using mapping. Differential Revision: http://reviews.llvm.org/D8782 llvm-svn: 237563
* AVX-512: Added intrinsics for ADDSS/D, MULSS/D, SUBSS/D, DIVSS/DElena Demikhovsky2015-05-182-2/+27
| | | | | | | | | instructions. These intrinsics are comming with rounding mode. Added intrinsics for MAXSS/D, MINSS/D - with and without sae. By Asaf Badouh (asaf.badouh@intel.com) llvm-svn: 237560
* fixed compilation warning/errorElena Demikhovsky2015-05-181-0/+1
| | | | llvm-svn: 237559
* AVX-512: Added patterns for scalar-to-vector broadcastElena Demikhovsky2015-05-181-0/+10
| | | | llvm-svn: 237558
* AVX-512: Added VBROADCASTF64X4, VBROADCASTF64X2, VBROADCASTI32X8, and other ↵Elena Demikhovsky2015-05-183-12/+61
| | | | | | | | instructions from this set Added encoding tests. llvm-svn: 237557
* [PowerPC] Add extra r2 read deps on @toc@l relocationsHal Finkel2015-05-184-0/+165
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If some commits are happy, and some commits are sad, this is a sad commit. It is sad because it restricts instruction scheduling to work around a binutils linker bug, and moreover, one that may never be fixed. On 2012-05-21, GCC was updated not to produce code triggering this bug, and now we'll do the same... When resolving an address using the ELF ABI TOC pointer, two relocations are generally required: one for the high part and one for the low part. Only the high part generally explicitly depends on r2 (the TOC pointer). And, so, we might produce code like this: .Ltmp526: addis 3, 2, .LC12@toc@ha .Ltmp1628: std 2, 40(1) ld 5, 0(27) ld 2, 8(27) ld 11, 16(27) ld 3, .LC12@toc@l(3) rldicl 4, 4, 0, 32 mtctr 5 bctrl ld 2, 40(1) And there is nothing wrong with this code, as such, but there is a linker bug in binutils (https://sourceware.org/bugzilla/show_bug.cgi?id=18414) that will misoptimize this code sequence to this: nop std r2,40(r1) ld r5,0(r27) ld r2,8(r27) ld r11,16(r27) ld r3,-32472(r2) clrldi r4,r4,32 mtctr r5 bctrl ld r2,40(r1) because the linker does not know (and does not check) that the value in r2 changed in between the instruction using the .LC12@toc@ha (TOC-relative) relocation and the instruction using the .LC12@toc@l(3) relocation. Because it finds these instructions using the relocations (and not by scanning the instructions), it has been asserted that there is no good way to detect the change of r2 in between. As a result, this bug may never be fixed (i.e. it may become part of the definition of the ABI). GCC was updated to add extra dependencies on r2 to instructions using the @toc@l relocations to avoid this problem, and we'll do the same here. This is done as a separate pass because: 1. These extra r2 dependencies are not really properties of the instructions, but rather due to a linker bug, and maybe one day we'll be able to get rid of them when targeting linkers without this bug (and, thus, keeping the logic centralized here will make that straightforward). 2. There are ISel-level peephole optimizations that propagate the @toc@l relocations to some user instructions, and so the exta dependencies do not apply only to a fixed set of instructions (without undesirable definition replication). The test case was reduced with the help of bugpoint, with minimal cleaning. I'm looking forward to our upcoming MI serialization support, and with that, much better tests can be created. llvm-svn: 237556
* AVX-512: fixed extended load to 512-bit registerElena Demikhovsky2015-05-171-2/+2
| | | | llvm-svn: 237537
* AVX-512: fixed a bug in mask operations - (i1 1) patternElena Demikhovsky2015-05-171-2/+2
| | | | | | | Filling k-reg with all-ones value was wrong, (i1 1) should switch on only one bit in mask register llvm-svn: 237536
* [x86] Distinguish the 'o', 'v', 'X', and 'i' inline assembly memory constraints.Daniel Sanders2015-05-162-3/+16
| | | | | | | | | | | | | | | | | | | | | | Summary: But still handle them the same way since I don't know how they differ on this target. Of these, 'o' and 'v' are not tested but were already implemented. I'm not sure why 'i' is required for X86 since it's supposed to be an immediate constraint rather than a memory constraint. A test asserts without it so I've included it for now. No functional change intended. Reviewers: nadav Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8254 llvm-svn: 237517
* MC: Use MCSymbol in RelAndSymbol, NFCDuncan P. N. Exon Smith2015-05-164-22/+14
| | | | | | Switch from `MCSymbolData` to `MCSymbol`. llvm-svn: 237502
* [PPC64] Add vector pack/unpack support from ISA 2.07Bill Schmidt2015-05-164-2/+93
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the following new instructions in the Power ISA 2.07: vpksdss vpksdus vpkudus vpkudum vupkhsw vupklsw These instructions are available through the vec_packs, vec_packsu, vec_unpackh, and vec_unpackl built-in interfaces. These are lane-sensitive instructions, so the built-ins have different implementations for big- and little-endian, and the instructions must be marked as killing the vector swap optimization for now. The first three instructions perform saturating pack operations. The fourth performs a modulo pack operation, which means it can be represented with a vector shuffle, and conversely the appropriate vector shuffles may cause this instruction to be generated. The other instructions are only generated via built-in support for now. Appropriate tests have been added. There is a companion patch to clang for the rest of this support. llvm-svn: 237499
* MC: Change MCFragment::Atom to an MCSymbol, NFCDuncan P. N. Exon Smith2015-05-162-32/+41
| | | | | | | Change `MCFragment::Atom` from an `MCSymbolData` to an `MCSymbol`, moving in the direction of removing the back-pointer. llvm-svn: 237497
* Remove MCAssembler.h include from MCStreamer.h and fix users of MCStreamer.hPete Cooper2015-05-154-0/+4
| | | | llvm-svn: 237483
* Remove 3 includes from MCInstrDesc.h and explicitly include them where neededPete Cooper2015-05-1513-0/+20
| | | | llvm-svn: 237481
* [X86] Use a better sentinel offset for the FrameAddr indexDavid Majnemer2015-05-151-1/+1
| | | | | | | | | Other pieces of CodeGen want to negate frame object offsets to account for architectures where the stack grows down. Our object is a pseudo object so it's offset doesn't matter. However, we shouldn't choose an offset which results in undefined behavior if you negate it. llvm-svn: 237474
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