summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* Fix pointer info on PPC byval storesHal Finkel2014-01-211-6/+5
| | | | | | | | | | | For PPC64 SVR (and Darwin), the stores that take byval aggregate parameters from registers into the stack frame had MachinePointerInfo objects with incorrect offsets. These offsets are relative to the object itself, not to the stack frame base. This fixes self hosting on PPC64 when compiling with -enable-aa-sched-mi. llvm-svn: 199763
* [mips][sched] Split IILoad into II_L[BHWD], II_L[BHW]U, II_L[WD][LR], and ↵Daniel Sanders2014-01-215-31/+52
| | | | | | | | II_RESTORE No functional change since the InstrItinData's have been duplicated. llvm-svn: 199749
* [mips][sched] Split IIFmoveC1 into II_M[FT]C1, II_M[FT]HC1, II_DM[FT]C1Daniel Sanders2014-01-213-12/+22
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199748
* [mips][sched] Split IIFStore into II_S[WD]C1, and II_S[WDU]XC1Daniel Sanders2014-01-213-14/+22
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199747
* [NVPTX] Add missing patterns for div.approx with immediate denominatorJustin Holewinski2014-01-211-0/+12
| | | | llvm-svn: 199746
* [mips][sched] Split IIFLoad into II_L[WD]C1, and II_L[WDU]XC1Daniel Sanders2014-01-213-16/+23
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199743
* [mips][sched] Removed IIFrecipFsqrtStep. No instructions use it.Daniel Sanders2014-01-211-2/+0
| | | | llvm-svn: 199742
* [mips][sched] Renamed II_FsqrtSingle and II_FsqrtDouble to II_SQRT_S and ↵Daniel Sanders2014-01-213-10/+10
| | | | | | | | II_SQRT_D respectively No functional change llvm-svn: 199741
* [mips][sched] Renamed II_FdivSingle and II_FdivDouble to II_DIV_S and ↵Daniel Sanders2014-01-213-8/+8
| | | | | | | | II_DIV_D respectively No functional change llvm-svn: 199738
* [mips][sched] Split IIFmulDouble into II_MUL_D, II_MADD_D, II_MSUB_D, ↵Daniel Sanders2014-01-213-18/+26
| | | | | | | | II_NMADD_D, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199737
* [mips][sched] Split IIFmulSingle into II_MUL_S, II_MADD_S, II_MSUB_S, ↵Daniel Sanders2014-01-213-12/+20
| | | | | | | | II_NMADD_S, and II_NMSUB_S No functional change since the InstrItinData's have been duplicated. llvm-svn: 199734
* [mips][sched] Split IIFadd into II_ADD_[DS], II_SUB_[DS]Daniel Sanders2014-01-213-10/+16
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199732
* [mips][sched] Split IIFcmp into II_C_CC_[SD]Daniel Sanders2014-01-213-32/+37
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199728
* [mips][sched] Split IIFmove into II_C[FT]C1, II_MOV[FNTZ]_[SD], II_MOV_[SD]Daniel Sanders2014-01-214-43/+65
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199727
* [mips][sched] Split IIFcvt into II_(ROUND|TRUNC|CEIL|FLOOR|CVT), II_ABS, II_NEGDaniel Sanders2014-01-213-63/+75
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199722
* [mips][sched] Split IIslt into II_SLT_SLTU, II_SLTI_SLTIUDaniel Sanders2014-01-212-3/+4
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199719
* ARM IAS: add support for .unwind_raw directiveSaleem Abdulrasool2014-01-213-0/+116
| | | | | | | | | | | | This implements the unwind_raw directive for the ARM IAS. The unwind_raw directive takes the form of a stack offset value followed by one or more bytes representing the opcodes to be emitted. The opcode emitted will interpreted as if it were assembled by the opcode assembler via the standard unwinding directives. Thanks to Logan Chien for an extra test! llvm-svn: 199707
* ARM IAS: support .personalityindexSaleem Abdulrasool2014-01-213-7/+109
| | | | | | | | | | | | | The .personalityindex directive is equivalent to the .personality directive with the ARM EABI personality with the specific index (0, 1, 2). Both of these directives indicate personality routines, so enhance the personality directive handling to take into account personalityindex. Bonus fix: flush the UnwindContext at the beginning of a new function. Thanks to Logan Chien for additional tests! llvm-svn: 199706
* [AArch64 NEON] Fix a bug caused by undef lane when generating VEXT.Kevin Qin2014-01-211-15/+21
| | | | | | | | It was commited as r199628 but reverted in r199628 as causing regression test failed. It's because of old vervsion of patch I used to commit. Sorry for mistake. llvm-svn: 199704
* To allow the X86 verbose assembly to print its informative commentsKevin Enderby2014-01-211-44/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | when used with symbolic disassembly, add a check that the operand is an immediate and has not been symbolicated to MCExpr operand. I’m trying to enable the ‘C’ disassembly API option LLVMDisassembler_Option_SetInstrComments for darwin’s otool(1) that uses the llvm disassembler API. The problem is that the disassembler API can change an immediate operand to an MCExpr operand if it symbolicates it with the call backs. And if it does the code in llvm::EmitAnyX86InstComments() will crash when it assumes these operands are immediates. The fix for this is very straight forward to just protect the call to getImm() with a check of isImm(). So if the immediate for an instruction is symbolicated it simply doesn’t get the X86 verbose assembly comments: % otool -tV test_asm.o test_asm.o: (__TEXT,__text) section _t1: 0000000000000000 vpshufd $_t1, %xmm1, %xmm0 0000000000000005 retq 0000000000000006 nopw %cs:_t1(%rax,%rax) _t2: 0000000000000010 vpshufd $-0x1, %xmm0, %xmm0 ## xmm0 = xmm0[3,3,3,3] 0000000000000015 retq 0000000000000016 nopw %cs:_t1(%rax,%rax) _t3: 0000000000000020 vpshufd $_t1, %xmm1, %xmm0 0000000000000025 retq 0000000000000026 nopw %cs:_t1(%rax,%rax) _t4: 0000000000000030 vpshufd $0x2d, %xmm0, %xmm0 ## xmm0 = xmm0[1,3,2,0] 0000000000000035 retq The fact that the immediate $0x0 is being symbolicated at all in this case is a different problem which my next patch will address. rdar://10989286 llvm-svn: 199697
* [X86] Teach how to combine a vselect into a movss/movsdAndrea Di Biagio2014-01-201-0/+35
| | | | | | | | | | | | | | | | | | | Add target specific rules for combining vselect dag nodes into movss/movsd when possible. If the vector type of the vselect dag node in input is either MVT::v4i13 or MVT::v4f32, then try to fold according to rules: 1) fold (vselect (build_vector (0, -1, -1, -1)), A, B) -> (movss A, B) 2) fold (vselect (build_vector (-1, 0, 0, 0)), A, B) -> (movss B, A) If the vector type of the vselect dag node in input is either MVT::v2i64 or MVT::v2f64 (and we have SSE2), then try to fold according to rules: 3) fold (vselect (build_vector (0, -1)), A, B) -> (movsd A, B) 4) fold (vselect (build_vector (-1, 0)), A, B) -> (movsd B, A) llvm-svn: 199683
* Debug info: On ARM ensure that all __TEXT sections come before theAdrian Prantl2014-01-201-0/+7
| | | | | | | | | optional DWARF sections, so compiling with -g does not result in different code being generated for PC-relative loads. This is reapplying a diet r197922 (__TEXT-only). llvm-svn: 199681
* Revert "Debug info: On ARM ensure that the data sections come before the"Adrian Prantl2014-01-201-13/+0
| | | | | | | | | Cut back on the cargo cult. The order of __DATA sections doesn't affect generated code. This reverts commit r197922. llvm-svn: 199680
* Remove the useless pseudo instructions VDUPfdf and VDUPfqf, replacing them ↵James Molloy2014-01-202-31/+6
| | | | | | with patterns to match VDUPLN. llvm-svn: 199675
* [x86] Fix disassembly of MOV16ao16 et al.David Woodhouse2014-01-201-2/+0
| | | | | | | | | | The addition of IC_OPSIZE_ADSIZE in r198759 wasn't quite complete. It also turns out to have been unnecessary. The disassembler handles the AdSize prefix for itself, and doesn't care about the difference between (e.g.) MOV8ao8 and MOB8ao8_16 definitions. So just let them coexist and don't worry about it. llvm-svn: 199654
* [x86] Fix 16-bit disassembly of JCXZ/JECXZDavid Woodhouse2014-01-201-0/+19
| | | | llvm-svn: 199653
* [x86] Rename MOVSD/STOSD/LODSD/OUTSD to MOVSL/STOSL/LODSL/OUTSLDavid Woodhouse2014-01-201-5/+5
| | | | | | | | The disassembler has a special case for 'L' vs. 'W' in its heuristic for checking for 32-bit and 16-bit equivalents. We could expand the heuristic, but better just to be consistent in using the 'L' suffix. llvm-svn: 199652
* [x86] Fix disassembly of callw instructionDavid Woodhouse2014-01-201-6/+4
| | | | | | | Not quite sure why this was marked isAsmParserOnly, but it means that the disassembler can't see it either. llvm-svn: 199651
* [x86] Fix 16-bit handling of OpSize bitDavid Woodhouse2014-01-201-3/+5
| | | | | | | | | | When disassembling in 16-bit mode the meaning of the OpSize bit is inverted. Instructions found in the IC_OPSIZE context will actually *not* have the 0x66 prefix, and instructions in the IC context will have the 0x66 prefix. Make use of the existing special-case handling for the 0x66 prefix being in the wrong place, to cope with this. llvm-svn: 199650
* [x86] Infer disassembler mode from SubtargetInfo feature bitsDavid Woodhouse2014-01-202-16/+24
| | | | | | | | | | | | Aside from cleaning up the code, this also adds support for the -code16 environment and actually enables the MODE_16BIT mode that was previously not accessible. There is no point adding any testing for 16-bit yet though; basically nothing will work because we aren't handling the OpSize prefix correctly for 16-bit mode. llvm-svn: 199649
* [x86] Support i386-*-*-code16 triple for emitting 16-bit codeDavid Woodhouse2014-01-202-3/+8
| | | | llvm-svn: 199648
* ARM: add tlsldo relocationKai Nacke2014-01-201-0/+3
| | | | | | | | | Add support for the symbol(tlsldo) relocation. This is required in order to solve PR18554. Reviewed by R. Golin, A. Korobeynikov. llvm-svn: 199644
* [ARM] Do not generate Tag_DIV_use=AllowDIVExt when hardware div is ↵Artyom Skrobov2014-01-201-6/+8
| | | | | | non-optional: it should have the default value of AllowDIVIfExists llvm-svn: 199638
* Revert r199628: "[AArch64 NEON] Fix a bug caused by undef lane when ↵Chandler Carruth2014-01-201-21/+15
| | | | | | | | generating VEXT." This test fails the newly added regression tests. llvm-svn: 199631
* [AArch64 NEON] Fix a bug caused by undef lane when generating VEXT.Kevin Qin2014-01-201-15/+21
| | | | llvm-svn: 199628
* [AArch64 NEON] Accept both #0.0 and #0 for comparing with floating point ↵Kevin Qin2014-01-202-14/+74
| | | | | | | | | | zero in asm parser. For FCMEQ, FCMGE, FCMGT, FCMLE and FCMLT, floating point zero will be printed as #0.0 instead of #0. To support the history codes using #0, we consider to let asm parser accept both #0.0 and #0. llvm-svn: 199621
* Move the retrieval of VT after all of the early exits from PerformOrCombine ↵Michael Gottesman2014-01-191-1/+1
| | | | | | that do not use VT. NFC. llvm-svn: 199612
* ARM ELF: ensure that the tag types are correctedSaleem Abdulrasool2014-01-191-0/+3
| | | | | | | | Ensure that the tag types are reflected on a replacement. This is particularly important for the compatibility tag which has multiple representations where the last definition wins. llvm-svn: 199577
* ARM: update build attributes for ABI r2.09Saleem Abdulrasool2014-01-191-2/+2
| | | | | | | Update names for the names as per the current ABI errata. Mark deprecated tags as such. llvm-svn: 199576
* Move ARM build attributes into SupportSaleem Abdulrasool2014-01-196-278/+4
| | | | | | | | | | | | This moves the ARM build attributes definitions and support routines into the Support library. The support routines simply permit the conversion of the value to and from a string representation. The movement is prompted in order to permit access to the constants and string representations from readobj in order to facilitate decoding of the attributes section. llvm-svn: 199575
* ARM IAS: remove unnecessary special caseSaleem Abdulrasool2014-01-191-1/+1
| | | | | | | Tag_nodefaults is even and greater than 32 and thus does not need the special check to fall into the correct category. llvm-svn: 199574
* ARM: Let the assembler reject v5 instructions in v4 mode.Benjamin Kramer2014-01-181-1/+2
| | | | | | PR18524. llvm-svn: 199559
* Add two new calling conventions for runtime callsJuergen Ributzka2014-01-172-0/+22
| | | | | | | | | | | | | | This patch adds two new target-independent calling conventions for runtime calls - PreserveMost and PreserveAll. The target-specific implementation for X86-64 is defined as following: - Arguments are passed as for the default C calling convention - The same applies for the return value(s) - PreserveMost preserves all GPRs - except R11 - PreserveAll preserves all GPRs and all XMMs/YMMs - except R11 Reviewed by Lang and Philip llvm-svn: 199508
* [mips][msa] Correct pattern for LSADaniel Sanders2014-01-171-2/+2
| | | | | | | | | | | | | | Summary: $rs and $rt were the wrong way round in the .td and the testcase wasn't strict enough to detect the mistake. Reviewers: matheusalmeida Reviewed By: matheusalmeida Differential Revision: http://llvm-reviews.chandlerc.com/D2554 llvm-svn: 199498
* [mips] Split IIIdiv int II_DIV, II_DIVU, II_DDIV, and II_DDIVUDaniel Sanders2014-01-174-12/+22
| | | | | | No functional change since the InstrItinData's were duplicated llvm-svn: 199497
* [mips][sched] Split IIImul and IIImult into subclasses.Daniel Sanders2014-01-174-31/+46
| | | | | | | | | IIImul -> II_MUL IIImult -> II_MULT, II_MULTU, II_MADD, II_MADDU, II_MSUB, II_MSUBU, II_DMULT, II_DMULTU No functional change since the InstrItinData's have been duplicated. llvm-svn: 199495
* [mips][sched] Split IIHiLo into II_MFHI_MFLO and II_MTHI_MTLODaniel Sanders2014-01-172-7/+10
| | | | | | No functional change since the InstrItinData's have been duplicated. llvm-svn: 199493
* Add MLA alias for ARMv4 support.Renato Golin2014-01-171-9/+14
| | | | | | | | | | Fix MLA defs to use register class GPRnopc. Add encoding tests for multiply instructions. (Alias for MUL/SMLAL/UMLAL added by r199026.) Patch by Zhaoshi. llvm-svn: 199491
* [AArch64 NEON] Expand vector for UDIV/SDIV/UREM/SREM/FREM as neon doesn't ↵Kevin Qin2014-01-171-0/+55
| | | | | | support these operations. llvm-svn: 199485
* Switch a few instructions to use RI instead I so they don't require REX_W to ↵Craig Topper2014-01-173-19/+19
| | | | | | be explicitly specified. llvm-svn: 199479
OpenPOWER on IntegriCloud