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* Remove the Blackfin backend.Dan Gohman2011-10-2537-4415/+0
| | | | llvm-svn: 142880
* Remove the SystemZ backend.Dan Gohman2011-10-2437-6279/+0
| | | | llvm-svn: 142878
* Nuke dead code. Nothing generates the VLD1d64QPseudo_UPD instruction.Jim Grosbach2011-10-243-4/+0
| | | | llvm-svn: 142877
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-244-21/+33
| | | | | | Three entry register list variation. llvm-svn: 142876
* Don't crash on variable insertelement on ARM. PR10258.Eli Friedman2011-10-241-0/+11
| | | | llvm-svn: 142871
* ARMConstantPoolMBB::print should print BB number.Evan Cheng2011-10-241-0/+1
| | | | llvm-svn: 142867
* ARM assembly parsing and encoding for VLD1 w/ writeback.Jim Grosbach2011-10-242-0/+38
| | | | | | One and two length register list variants. llvm-svn: 142861
* ARM refactor am6offset usage for VLD1.Jim Grosbach2011-10-245-71/+181
| | | | | | | | Split am6offset into fixed and register offset variants so the instruction encodings are explicit rather than relying an a magic reg0 marker. Needed to being able to parse these. llvm-svn: 142853
* Add support to the old JIT for acquire/release loads and stores on x86. ↵Eli Friedman2011-10-241-9/+24
| | | | | | PR11207. llvm-svn: 142841
* Fix a NEON disassembly case that was broken in the recent refactorings. As ↵Owen Anderson2011-10-241-6/+0
| | | | | | more of this code gets refactored, a lot of these manual decoding hooks should get smaller and/or go away entirely. llvm-svn: 142817
* Change this overloaded use of Sched::Latency to be an overloadedDan Gohman2011-10-241-2/+2
| | | | | | use of Sched::ILP instead, as Sched::Latency is going away. llvm-svn: 142813
* Remove the explicit request for "Latency" scheduling from MSP430,Dan Gohman2011-10-241-1/+0
| | | | | | as the Latency scheduler is going away. llvm-svn: 142811
* Thumb2 LDM instructions can target PC. Make sure to encode it.Jim Grosbach2011-10-241-8/+4
| | | | | | PR11220 llvm-svn: 142801
* Add X86 SARX, SHRX, and SHLX instructions.Craig Topper2011-10-231-18/+32
| | | | llvm-svn: 142779
* Add X86 RORX instructionCraig Topper2011-10-235-0/+36
| | | | llvm-svn: 142741
* Add X86 MULX instruction for disassembler.Craig Topper2011-10-231-0/+24
| | | | llvm-svn: 142738
* Remove some duplicate specifying of neverHasSideEffects and mayLoad from X86 ↵Craig Topper2011-10-221-5/+5
| | | | | | multiply instructions. llvm-svn: 142737
* Move various generated tables into read-only memory, fixing up const ↵Benjamin Kramer2011-10-223-11/+12
| | | | | | correctness along the way. llvm-svn: 142726
* Fix pr11193.Nadav Rotem2011-10-221-3/+0
| | | | | | | SHL inserts zeros from the right, thus even when the original sign_extend_inreg value was of 1-bit, we need to sra. llvm-svn: 142724
* The different flavors of ARM have different valid subsets of registers. CheckBill Wendling2011-10-221-3/+13
| | | | | | | that the set of callee-saved registers is correct for the specific platform. <rdar://problem/10313708> & ctor_dtor_count & ctor_dtor_count-2 llvm-svn: 142706
* Assembly parsing for 4-register sequential variant of VLD2.Jim Grosbach2011-10-213-36/+18
| | | | llvm-svn: 142704
* Assembly parsing for 2-register sequential variant of VLD2.Jim Grosbach2011-10-214-30/+46
| | | | llvm-svn: 142691
* Assembly parsing for 4-register variant of VLD1.Jim Grosbach2011-10-216-31/+38
| | | | llvm-svn: 142682
* Assembly parsing for 3-register variant of VLD1.Jim Grosbach2011-10-216-22/+37
| | | | llvm-svn: 142675
* ARM VLD parsing and encoding.Jim Grosbach2011-10-216-247/+276
| | | | | | | | | | | | Next step in the ongoing saga of NEON load/store assmebly parsing. Handle VLD1 instructions that take a two-register register list. Adjust the instruction definitions to only have the single encoded register as an operand. The super-register from the pseudo is kept as an implicit def, so passes which come after pseudo-expansion still know that the instruction defines the other subregs. llvm-svn: 142670
* Don't automatically set the "fc" bits on MSR instructions if the user didn't ↵Owen Anderson2011-10-211-3/+7
| | | | | | ask for them. This is a divergence from gas' behavior, but it is correct per the documentation and allows us to forge ahead with roundtrip testing. llvm-svn: 142669
* Nuke an #if0 that got accidentally left in.Jim Grosbach2011-10-211-31/+0
| | | | llvm-svn: 142658
* whitespace.Jim Grosbach2011-10-211-1/+1
| | | | llvm-svn: 142657
* Remove some outdated comments.Jim Grosbach2011-10-211-11/+11
| | | | llvm-svn: 142653
* Remove intrinsics for X86 BLSI, BLSMSK, and BLSR intrinsics and replace with ↵Craig Topper2011-10-213-11/+71
| | | | | | custom isel lowering code. llvm-svn: 142642
* Fix unused variable warning.Richard Smith2011-10-211-1/+1
| | | | llvm-svn: 142630
* Revert r142618, r142622, and r142624, which were based on an incorrect ↵Owen Anderson2011-10-201-42/+4
| | | | | | reading of the ARMv7 docs. llvm-svn: 142626
* Disable the PPC hazard recognizer. It currently only supportsDan Gohman2011-10-201-2/+8
| | | | | | top-down scheduling and top-down scheduling is going away. llvm-svn: 142621
* Separate out ARM MSR instructions into M-class versions and AR-class ↵Owen Anderson2011-10-201-4/+42
| | | | | | versions. This fixes some roundtripping failures. llvm-svn: 142618
* Add missing operand. <rdar://problem/10313323>Bill Wendling2011-10-201-1/+2
| | | | llvm-svn: 142615
* Haven't yet found a nice way to handle TargetData verification in theLang Hames2011-10-201-25/+88
| | | | | | | | AsmParser. This patch adds validation for target data layout strings upon construction of TargetData objects. An attempt to construct a TargetData object from a malformed string will trigger an assertion. llvm-svn: 142605
* Tidy up. Trailing whitespace.Jim Grosbach2011-10-201-2/+2
| | | | llvm-svn: 142591
* ARM VLD1/VST1 (one register, no writeback) assembly parsing and encoding.Jim Grosbach2011-10-201-4/+4
| | | | llvm-svn: 142583
* ARM VTBX (one register) assembly parsing and encoding.Jim Grosbach2011-10-201-3/+3
| | | | llvm-svn: 142581
* Revert 142337. Thumb1 still doesn't support dynamic stack realignment. :(Chad Rosier2011-10-203-32/+11
| | | | llvm-svn: 142557
* Fix TLS lowering bug. The CopyFromReg must be glued to the TLSCALL. ↵Evan Cheng2011-10-191-1/+2
| | | | | | rdar://10291355 llvm-svn: 142550
* Use literal pool loads instead of MOVW/MOVT for materializing global ↵James Molloy2011-10-191-3/+6
| | | | | | | | | | | | | | addresses when optimizing for size. On spec/gcc, this caused a codesize improvement of ~1.9% for ARM mode and ~4.9% for Thumb(2) mode. This is codesize including literal pools. The pools themselves doubled in size for ARM mode and quintupled for Thumb mode, leaving suggestion that there is still perhaps redundancy in LLVM's use of constant pools that could be decreased by sharing entries. Fixes PR11087. llvm-svn: 142530
* Make sure we emit the 'movw' and 'movt' only if it's supported. Otherwise, ↵Bill Wendling2011-10-191-5/+27
| | | | | | use a constant pool. llvm-svn: 142485
* Remove some dead code.Bill Wendling2011-10-191-6/+0
| | | | llvm-svn: 142484
* Rename PEXTR to PEXT. Add intrinsics for BMI instructions.Craig Topper2011-10-191-24/+47
| | | | llvm-svn: 142480
* Emit the MOVT instruction only if the # LPads is > 64K.Bill Wendling2011-10-181-10/+20
| | | | llvm-svn: 142460
* For Thumb mode, we need to use a constant pool if the value is too large to beBill Wendling2011-10-181-3/+20
| | | | | | used with the CMP instruction. llvm-svn: 142458
* Revert "Turn on the vzeroupper pass by default."Eric Christopher2011-10-181-1/+1
| | | | | | This reverts commit 494f7ac3e8d2ab3d94e52317abf9c42a949fe1f3. llvm-svn: 142455
* ARM VTBL (one register) assembly parsing and encoding.Jim Grosbach2011-10-184-3/+101
| | | | llvm-svn: 142441
* Use the integer compare when the value is small enough. Use the "move into aBill Wendling2011-10-181-2/+17
| | | | | | | register and then compare against that" method when it's too large. We have to move the value into the register in the "movw, movt" pair of instructions. llvm-svn: 142440
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