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* [X86] Simplify X87 stackifier pass.Akira Hatanaka2014-08-017-308/+196
| | | | | | | | | | | | | | | | | | | Stop using ST registers for function returns and inline-asm instructions and use FP registers instead. This allows removing a large amount of code in the stackifier pass that was needed to track register liveness and handle copies between ST and FP registers and function calls returning floating point values. It also fixes a bug which manifests when an ST register defined by an inline-asm instruction was live across another inline-asm instruction, as shown in the following sequence of machine instructions: 1. INLINEASM <es:frndint> $0:[regdef], %ST0<imp-def,tied5> 2. INLINEASM <es:fldcw $0> 3. %FP0<def> = COPY %ST0 <rdar://problem/16952634> llvm-svn: 214580
* [SDAG] MorphNodeTo recursively deletes dead operands of the oldChandler Carruth2014-08-012-9/+9
| | | | | | | | | | | | | fromulation of the node, which isn't really the desired behavior from within the combiner or legalizer, but is necessary within ISel. I've added a hopefully helpful comment and fixed the only two places where this took place. Yet another step toward the combiner and legalizer not needing to use update listeners with virtual calls to manage the worklists behind legalization and combining. llvm-svn: 214574
* Revert "R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cpp"Tom Stellard2014-08-012-42/+37
| | | | | | | | This reverts commit r214566. I did not mean to commit this yet. llvm-svn: 214572
* R600/SI: Remove leftover debugging codeTom Stellard2014-08-011-2/+0
| | | | llvm-svn: 214569
* R600: Move code for generating REGISTER_LOAD into R600ISelLowering.cppTom Stellard2014-08-012-37/+42
| | | | | | | SI doesn't use REGISTER_LOAD anymore, but it was still hitting this code path for 8-bit and 16-bit private loads. llvm-svn: 214566
* Add a non-const subtarget returning function to the target machineEric Christopher2014-08-015-5/+16
| | | | | | | | | so that we can use it to get the old-style JIT out of the subtarget. This code should be removed when the old-style JIT is removed (imminently). llvm-svn: 214560
* MS inline asm: Use memory constraints for functions instead of registersReid Kleckner2014-08-011-9/+21
| | | | | | | | | | | | | | | | | | | | | | This is consistent with how we parse them in a standalone .s file, and inline assembly shouldn't differ. This fixes errors about requiring more registers than available in cases like this: void f(); void __declspec(naked) g() { __asm pusha __asm call f __asm popa __asm ret } There are no registers available to pass the address of 'f' into the asm blob. The asm should now directly call 'f'. Tests will land in Clang shortly. llvm-svn: 214550
* [FastISel][AArch64] Fold offset into the memory operation.Juergen Ributzka2014-08-011-0/+7
| | | | | | | | | | | | Fold simple offsets into the memory operation: add x0, x0, #8 ldr x0, [x0] --> ldr x0, [x0, #8] Fixes <rdar://problem/17887945>. llvm-svn: 214545
* Add support for StackMap section for ELF/Linux systemsPhilip Reames2014-08-011-0/+2
| | | | | | | | | | This patch adds code to emits the StackMap section on ELF systems. This section is required to support llvm.experimental.stackmap and llvm.experimental.patchpoint intrinsics. Reviewers: ributzka, echristo Differential Revision: http://reviews.llvm.org/D4574 llvm-svn: 214538
* [FastISel][AArch64] Add branch weights.Juergen Ributzka2014-08-011-5/+38
| | | | | | | | | Add branch weights to branch instructions, so that the following passes can optimize based on it (i.e. basic block ordering). Fixes <rdar://problem/17887137>. llvm-svn: 214537
* [FastISel][ARM] Do not emit stores for undef arguments.Juergen Ributzka2014-08-011-0/+6
| | | | | | | | This is a followup patch for r214366, which added the same behavior to the AArch64 and X86 FastISel code. This fix reproduces the already existing behavior of SelectionDAG in FastISel. llvm-svn: 214531
* Add missing breaks to AArch64InstrInfo::isGPRCopyRenato Golin2014-08-011-0/+3
| | | | llvm-svn: 214528
* R600/SI: Don't display GDS bit for read2Matt Arsenault2014-08-011-1/+1
| | | | | | | This isn't displayed for any other instructions anymore, and isn't ever used. llvm-svn: 214523
* [AArch64] Generate tbz/tbnz when comparing against zero.Chad Rosier2014-08-011-10/+16
| | | | | | | | | | | | | | | | | The tbz/tbnz checks the sign bit to convert op w1, w1, w10 cmp w1, #0 b.lt .LBB0_0 to op w1, w1, w10 tbnz w1, #31, .LBB0_0 Differential Revision: http://reviews.llvm.org/D4440 llvm-svn: 214518
* [PowerPC] PR20280 - Slots for byval parameters are not immutableUlrich Weigand2014-08-011-1/+1
| | | | | | | | | Found by inspection while looking at PR20280: code would mark slots in the parameter save area where a byval parameter is passed as "immutable". This is not correct since code is allowed to modify byval parameters in place in the parameter save area. llvm-svn: 214517
* Allow only disassembling of M-class MSR masks that the assembler knows how ↵James Molloy2014-08-011-1/+47
| | | | | | | | | | to assemble back. Note: The current code in DecodeMSRMask() rejects the unpredictable A/R MSR mask '0000' with Fail. The code in the patch follows this style and rejects unpredictable M-class MSR masks also with Fail (instead of SoftFail). If SoftFail is preferred in this case then additional changes to ARMInstPrinter (to print non-symbolic masks) and ARMAsmParser (to parse non-symbolic masks) will be needed. Patch by Petr Pavlu! llvm-svn: 214505
* Improve some const-correctness to remove a -Wcast-qual warning. No ↵Aaron Ballman2014-08-013-4/+5
| | | | | | functional changes intended. llvm-svn: 214503
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM ↵Tilmann Scheller2014-08-011-1/+7
| | | | | | | | LDRB/LDRSB instructions. The ARM ARM prohibits LDRB/LDRSB instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214500
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM ↵Tilmann Scheller2014-08-011-1/+5
| | | | | | | | LDRH/LDRSH instructions. The ARM ARM prohibits LDRH/LDRSH instructions with writeback into the source register. With this commit this constraint is now enforced and we stop assembling LDRH/LDRSH instructions with unpredictable behavior. llvm-svn: 214499
* [ARM] Make the assembler reject unpredictable pre/post-indexed ARM LDR ↵Tilmann Scheller2014-08-011-0/+13
| | | | | | | | instructions. The ARM ARM prohibits LDR instructions with writeback into the destination register. With this commit this constraint is now enforced and we stop assembling LDR instructions with unpredictable behavior. llvm-svn: 214498
* [mips][PR19612] Fix va_arg for big-endian mode.Daniel Sanders2014-08-012-2/+68
| | | | | | | | | | | | | | | | | | Summary: Big-endian mode was not correctly adjusting the offset for types smaller than an ABI slot. Fixes PR19612 Reviewers: dsanders Reviewed By: dsanders Subscribers: sstankovic, llvm-commits Differential Revision: http://reviews.llvm.org/D4556 llvm-svn: 214493
* [PowerPC] Generate unaligned vector loads using intrinsics instead of ↵Hal Finkel2014-08-011-50/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | regular loads Altivec vector loads on PowerPC have an interesting property: They always load from an aligned address (by rounding down the address actually provided if necessary). In order to generate an actual unaligned load, you can generate two load instructions, one with the original address, one offset by one vector length, and use a special permutation to extract the bytes desired. When this was originally implemented, I generated these two loads using regular ISD::LOAD nodes, now marked as aligned. Unfortunately, there is a problem with this: The alignment of a load does not contribute to its identity, and SDNodes are uniqued. So, imagine that we have some unaligned load, L1, that is not aligned. The routine will create two loads, L1(aligned) and (L1+16)(aligned). Further imagine that there had already existed a load (L1+16)(unaligned) with the same chain operand as the load L1. When (L1+16)(aligned) is created as part of the lowering of L1, this load *is* also the (L1+16)(unaligned) node, just now marked as aligned (because the new alignment overwrites the old). But the original users of (L1+16)(unaligned) now get the data intended for the permutation yielding the data for L1, and (L1+16)(unaligned) no longer exists to get its own permutation-based expansion. This was PR19991. A second potential problem has to do with the MMOs on these loads, which can be used by AA during instruction scheduling to break chain-based dependencies. If the new "aligned" loads get the MMO from the original unaligned load, this does not represent the fact that it will load data from below the original address. Normally, this would not matter, but this load might be combined with another load pair for a previous vector, and then the dependency on the otherwise- ignored lower bytes can matter. To fix both problems, instead of generating the necessary loads using regular ISD::LOAD instructions, ppc_altivec_lvx intrinsics are used instead. These are provided with MMOs with a conservative address range. Unfortunately, I no longer have a failing test case (since PR19991 was reported, other changes in CodeGen have forced this bug back into hiding it again). Nevertheless, this should fix the underlying problem. llvm-svn: 214481
* R600/SI: Fix build warningTom Stellard2014-08-011-1/+1
| | | | llvm-svn: 214475
* [FastISel][AArch64] Fix the immediate versions of the ↵Juergen Ributzka2014-08-011-48/+49
| | | | | | | | | | | | {s|u}{add|sub}.with.overflow intrinsics. ADDS and SUBS cannot encode negative immediates or immediates larger than 12bit. This fix checks if the immediate version can be used under this constraints and if we can convert ADDS to SUBS or vice versa to support negative immediates. Also update the test cases to test the immediate versions. llvm-svn: 214470
* [PowerPC] Recognize consecutive memory accesses from intrinsicsHal Finkel2014-08-011-9/+63
| | | | | | | | | | | | | | | When generating unaligned vector loads, we need to search for other loads or stores nearby offset by one vector width. If we find one, then we know that we can safely generate another aligned load at that address. Otherwise, we must generate the next load using an offset of the vector width minus one byte (so we don't read off the end of the allocation if the base unaligned address happened to be aligned at runtime). We had previously done this using only other vector loads and stores, but did not consider the PowerPC-specific vector load/store intrinsics. Now we'll also consider vector intrinsics. By itself, this change is a feature enhancement, but is a necessary step toward fixing the underlying problem behind PR19991. llvm-svn: 214469
* MS inline asm: Fix null SMLoc when 'ptr' is missing after dword & coReid Kleckner2014-08-011-1/+1
| | | | | | | | This improves the diagnostics from the regular assembler, but more importantly it fixes an assertion when parsing inline assembly. Test landing in Clang. llvm-svn: 214468
* R600/SI: Do abs/neg folding with ComplexPatternsTom Stellard2014-08-0111-658/+1034
| | | | | | | | | | Abs/neg folding has moved out of foldOperands and into the instruction selection phase using complex patterns. As a consequence of this change, we now prefer to select the 64-bit encoding for most instructions and the modifier operands have been dropped from integer VOP3 instructions. llvm-svn: 214467
* R600/SI: Simplify and fix handling of VOP2 in SIInstrInfo::legalizeOperandsTom Stellard2014-08-012-28/+53
| | | | | | | | | | | | We were incorrectly assuming that all VOP2 instructions can read SGPRs in Src0, but this is not true for instructions that read carry-in from VCC. The old logic has been replaced with new logic which checks the defined register classes of the VOP2 instruction to determine whether or not to legalize the operands. llvm-svn: 214465
* R600/SI: Fold immediates when shrinking instructionsTom Stellard2014-08-013-12/+79
| | | | | | | This will prevent us from using extra MOV instructions once we prefer selecting 64-bit instructions. llvm-svn: 214464
* R600/SI: Fix incorrect commute operation in shrink instructions passTom Stellard2014-08-013-3/+16
| | | | | | | | We were commuting the instruction by still shrinking it using the original opcode. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 214463
* Add support for the X86 secure guard extensions instructions in assembler (SGX).Kevin Enderby2014-07-319-68/+110
| | | | | | | | | | | | | This allows assembling the two new instructions, encls and enclu for the SKX processor model. Note the diffs are a bigger than what might think, but to fit the new MRM_CF and MRM_D7 in things in the right places things had to be renumbered and shuffled down causing a bit more diffs. rdar://16228228 llvm-svn: 214460
* X86 MC: Don't crash on empty memory operand parensReid Kleckner2014-07-311-2/+4
| | | | | | | | Instead, create an absolute memory operand. Fixes PR20504. llvm-svn: 214457
* X86 MC: Reject invalid segment registers before a memory operand colonReid Kleckner2014-07-311-0/+3
| | | | | | Previously we would execute unreachable during object emission. llvm-svn: 214456
* Make sure no loads resulting from load->switch DAGCombine are marked invariantLouis Gerbarg2014-07-3112-23/+28
| | | | | | | | | | | | | | Currently when DAGCombine converts loads feeding a switch into a switch of addresses feeding a load the new load inherits the isInvariant flag of the left side. This is incorrect since invariant loads can be reordered in cases where it is illegal to reoarder normal loads. This patch adds an isInvariant parameter to getExtLoad() and updates all call sites to pass in the data if they have it or false if they don't. It also changes the DAGCombine to use that data to make the right decision when creating the new load. llvm-svn: 214449
* Fixing an -Woverloaded-virtual warnings by exposing the hidden virtual ↵Aaron Ballman2014-07-311-0/+1
| | | | | | function as well. No functional changes intended. llvm-svn: 214400
* Fixing a -Wcast-qual warning in GCC. No functional changes.Aaron Ballman2014-07-311-2/+2
| | | | llvm-svn: 214399
* [asan] Support x86 REP MOVS asm instrumentation.Evgeniy Stepanov2014-07-313-20/+153
| | | | | | Patch by Yuri Gorshenin. llvm-svn: 214395
* [FastISel][AArch64] Add basic bitcast support for conversion between float ↵Juergen Ributzka2014-07-311-0/+37
| | | | | | | | and int. Fixes <rdar://problem/17867078>. llvm-svn: 214389
* [FastISel][AArch64] Add sqrt intrinsic support.Juergen Ributzka2014-07-311-0/+19
| | | | | | Fixes <rdar://problem/17867067>. llvm-svn: 214388
* [FastISel][AArch64] Add MachO large code model support for function calls.Juergen Ributzka2014-07-311-10/+105
| | | | | | | | | Currently the large code model for MachO uses the GOT to make function calls. Emit the required adrp and ldr instructions to load the address from the GOT. Related to <rdar://problem/17733076>. llvm-svn: 214381
* Fix bit initializer which was one bit too long, but worked so long as we ↵Pete Cooper2014-07-311-1/+1
| | | | | | silently dropped the leading 0 llvm-svn: 214373
* Fix bit initializer which was one bit too long, but worked so long as we ↵Pete Cooper2014-07-311-1/+1
| | | | | | silently dropped the leading 0 llvm-svn: 214372
* [FastISel][AArch64 and X86] Don't emit stores for UNDEF arguments during ↵Juergen Ributzka2014-07-312-0/+9
| | | | | | | | | | function call lowering. UNDEF arguments are not ment to be touched - especially for the webkit_js calling convention. This fix reproduces the already existing behavior of SelectionDAG in FastISel. llvm-svn: 214366
* X86 asm parser: Avoid duplicating the list of aliased instructionsReid Kleckner2014-07-311-16/+11
| | | | | | No functional change. llvm-svn: 214364
* Add mtpid/mfpid for BookE.Joerg Sonnenberger2014-07-301-0/+3
| | | | llvm-svn: 214363
* Refactor TLBIVAX and add tlbsx.Joerg Sonnenberger2014-07-302-8/+10
| | | | llvm-svn: 214354
* X86 asm parser: Use a loop to disambiguate suffixes instead of copy pasteReid Kleckner2014-07-301-38/+20
| | | | | | | | | This works towards making the Intel syntax asm matcher use a completely different disambiguation strategy. No functional change. llvm-svn: 214352
* [FastISel][AArch64] Add select folding support for the XALU intrinsics.Juergen Ributzka2014-07-301-34/+36
| | | | | | | | | | | This improves the code generation for the XALU intrinsics when the condition is feeding a select instruction. This also updates and enables the XALU unit tests for FastISel. This fixes <rdar://problem/17831117>. llvm-svn: 214350
* [FastISel][AArch64] Add branch folding support for the XALU intrinsics.Juergen Ributzka2014-07-301-3/+77
| | | | | | | | | This improves the code generation for the XALU intrinsics when the condition is feeding a branch instruction. This is related to <rdar://problem/17831117>. llvm-svn: 214349
* [FastISel][AArch64] Add {s|u}{add|sub|mul}.with.overflow intrinsic support.Juergen Ributzka2014-07-301-0/+171
| | | | | | | | | | This commit adds support for the {s|u}{add|sub|mul}.with.overflow intrinsics. The unit tests for FastISel will be enabled in a later commit, once there is also branch and select folding support. This is related to <rdar://problem/17831117>. llvm-svn: 214348
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