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* [WebAssembly] Remove an unused data member. NFC.Dan Gohman2016-01-193-10/+7
| | | | llvm-svn: 258192
* [AArch64] Remove more dead code after r258093.Chad Rosier2016-01-191-12/+4
| | | | llvm-svn: 258191
* WebAssembly: mark known failure caused by r258125JF Bastien2016-01-191-0/+3
| | | | | | | The following test program triggers the assertion: https://github.com/gcc-mirror/gcc/blob/master/gcc/testsuite/gcc.c-torture/execute/20030916-1.c llvm-svn: 258182
* [AVX512] Adding VPERMT2B and VPERMI2B instruction .Michael Zuckerman2016-01-191-12/+22
| | | | | | Differential Revision: http://reviews.llvm.org/D16297 llvm-svn: 258161
* [opaque pointer types] [NFC] GEP: replace get(Pointer)ElementType uses with ↵Eduard Burtescu2016-01-191-1/+7
| | | | | | | | | | | | | | | | | | get{Source,Result}ElementType. Summary: GEPOperator: provide getResultElementType alongside getSourceElementType. This is made possible by adding a result element type field to GetElementPtrConstantExpr, which GetElementPtrInst already has. GEP: replace get(Pointer)ElementType uses with get{Source,Result}ElementType. Reviewers: mjacob, dblaikie Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D16275 llvm-svn: 258145
* [AVX512] Adding VPERMB instructionMichael Zuckerman2016-01-192-2/+19
| | | | | | Differential Revision: http://reviews.llvm.org/D16294 llvm-svn: 258144
* [WebAssembly] Rematerialize constants rather than hold them live in registers.Dan Gohman2016-01-194-40/+77
| | | | | | | | | Teach the register stackifier to rematerialize constants that have multiple uses instead of leaving them in registers. In the WebAssembly encoding, it's the same code size to materialize most constants as it is to read a value from a register. llvm-svn: 258142
* Typo.Chad Rosier2016-01-191-1/+1
| | | | llvm-svn: 258137
* [X86] Add support for "xlat m8"Marina Yatsina2016-01-191-0/+11
| | | | | | | | According to x86 spec "xlat m8" is a legal instruction and it is equivalent to "xlatb". Differential Revision: http://reviews.llvm.org/D15150 llvm-svn: 258135
* [X86] Adding support for missing variations of X86 string related instructionsMarina Yatsina2016-01-192-75/+203
| | | | | | | | | | | | | | | The following are legal according to X86 spec: ins mem, DX outs DX, mem lods mem stos mem scas mem cmps mem, mem movs mem, mem Differential Revision: http://reviews.llvm.org/D14827 llvm-svn: 258132
* [WebAssembly] Disable some WebAssembly-specific optimization passes at -O0.Dan Gohman2016-01-191-3/+6
| | | | llvm-svn: 258127
* [WebAssembly] Use the templated form of MachineFunction::getSubtarget(). NFC.Dan Gohman2016-01-192-5/+4
| | | | llvm-svn: 258126
* [X86][AVX512]fix dag & add intrinsics for fixupimmAsaf Badouh2016-01-195-17/+179
| | | | | | | | cover all width and types (pd/ps/sd/ss) of fixupimm instruction and inrtinsics Differential Revision: http://reviews.llvm.org/D16313 llvm-svn: 258124
* AMDGPU: Reduce 64-bit SRAsMatt Arsenault2016-01-182-0/+62
| | | | llvm-svn: 258096
* AMDGPU: Split 64-bit and of constant upMatt Arsenault2016-01-183-2/+70
| | | | | | | | | | This breaks the tests that were meant for testing 64-bit inline immediates, so move those to shl where they won't be broken up. This should be repeated for the other related bit ops. llvm-svn: 258095
* [AArch64] Remove unused arguments. NFC.Chad Rosier2016-01-181-7/+7
| | | | | | AFAICT, these have been unused since the initial backend import. llvm-svn: 258093
* AMDGPU: Generalize shl combineMatt Arsenault2016-01-181-8/+14
| | | | | | | Reduce 64-bit shl with constant > 32. We already special cased this for the == 32 case, but this also works for any >= 32 constant. llvm-svn: 258092
* AMDGPU: Reduce 64-bit lshr by constant to 32-bitMatt Arsenault2016-01-182-0/+45
| | | | | | 64-bit shifts are very slow on some subtargets. llvm-svn: 258090
* AMDGPU: Add subtarget feature for instruction ratesMatt Arsenault2016-01-184-9/+23
| | | | llvm-svn: 258085
* Fixed MSVC Win64 warning of implicit conversion of 32-bit shift to 64-bits.Simon Pilgrim2016-01-181-1/+1
| | | | llvm-svn: 258084
* [X86][AVX2] Broadcast subvectorsSimon Pilgrim2016-01-181-3/+21
| | | | | | | | AVX2 can only broadcast from the zero'th element of a vector, but if the broadcastable element is the zero'th element of a 128-bit subvector its advantageous to extract the subvector, broadcast from that and avoid the loading of shuffle mask data that would be needed for VPERMPS/VPERMD. The only exception being when the source type is 4f64 or 4i64 which can directly use the immediate shuffle VPERMPD/VPERMQ directly. Differential Revision: http://reviews.llvm.org/D16050 llvm-svn: 258081
* [Hexagon] Recognize more copy-equivalents in RDF optimizationsKrzysztof Parzyszek2016-01-181-14/+59
| | | | llvm-svn: 258076
* [RDF] Improvements to copy propagationKrzysztof Parzyszek2016-01-182-72/+145
| | | | | | | - Allow any instruction to define equality between registers. - Keep the DFG updated. llvm-svn: 258075
* [RDF] Improve compile-time performance of dead code eliminationKrzysztof Parzyszek2016-01-182-12/+42
| | | | llvm-svn: 258074
* [RDF] Allow unlinking ref nodes from data-flow chains onlyKrzysztof Parzyszek2016-01-183-14/+23
| | | | llvm-svn: 258073
* AVX512: Masked store intrinsic implementation.Igor Breger2016-01-183-29/+61
| | | | | | | | Implemented intrinsic for the follow instructions (store) : VMOVDQU8/16/32/64, VMOVDQA32/64, VMOVAPS/PD, VMOVUPS/PD. Differential Revision: http://reviews.llvm.org/D16271 llvm-svn: 258047
* Added Cannonlake processor to X86 TargetElena Demikhovsky2016-01-181-1/+37
| | | | | | Differential Revision: http://reviews.llvm.org/D16289 llvm-svn: 258046
* AVX512 : Change v8i1 bitconvert GR8 pattern, remove unnecessary movzbl ↵Igor Breger2016-01-181-1/+1
| | | | | | | | | | | | | | instruction. code example , previous implementation. movzbl %dil, %eax kmovw %eax, %k0 new code kmovw %edi, %k0 Differential Revision: http://reviews.llvm.org/D16287 llvm-svn: 258045
* [ARM] Operands for PKHTB alias should be swappedOliver Stannard2016-01-182-6/+6
| | | | | | | | | When the shift immediate is zero, PKHTB is an alias for PKHBT, but the order of the input operands needs to be swapped. Differential Revision: http://reviews.llvm.org/D16288 llvm-svn: 258044
* [opaque pointer types] [NFC] CallSite: use getFunctionType() instead of ↵Manuel Jacob2016-01-172-10/+3
| | | | | | | | | | | | | | going through PointerType::getElementType. Patch by Eduard Burtescu. Reviewers: dblaikie, mjacob Subscribers: dsanders, llvm-commits, dblaikie Differential Revision: http://reviews.llvm.org/D16273 llvm-svn: 258023
* [AVX512] adding AVXVBMI feature flagMichael Zuckerman2016-01-174-1/+11
| | | | | | | | | | The feature flag is for VPERMB,VPERMI2B,VPERMT2B and VPMULTISHIFTQB instructions. More about the instruction can be found in: hattps://software.intel.com/sites/default/files/managed/07/b7/319433-023.pdf Differential Revision: http://reviews.llvm.org/D16190 llvm-svn: 258012
* AVX512: Use MemIntrinsicSDNode to implement load/store intrinsic.Igor Breger2016-01-171-60/+76
| | | | | | Differential Revision: http://reviews.llvm.org/D16184 llvm-svn: 258009
* [AVX512] Adding VPERMW/D/Q VPERMPS/D Intrinsics Michael Zuckerman2016-01-171-0/+11
| | | | | | Differential Revision: http://reviews.llvm.org/D16189 llvm-svn: 258008
* [AVX512] Adding VPERMQ VPERMPD Intrinsics Michael Zuckerman2016-01-171-0/+4
| | | | | | Differential Revision: http://reviews.llvm.org/D16194 llvm-svn: 258006
* [X86][AVX] Enable extraction of upper 128-bit subvectors for 'half undef' ↵Simon Pilgrim2016-01-161-11/+28
| | | | | | | | | | shuffle lowering Added support for the extraction of the upper 128-bit subvectors for lower/upper half undef shuffles if it would reduce the number of extractions/insertions or avoid loads of AVX2 permps/permd shuffle masks. Minor follow up to D15477. llvm-svn: 258000
* GlobalValue: use getValueType() instead of getType()->getPointerElementType().Manuel Jacob2016-01-1613-28/+24
| | | | | | | | | | | | Reviewers: mjacob Subscribers: jholewinski, arsenm, dsanders, dblaikie Patch by Eduard Burtescu. Differential Revision: http://reviews.llvm.org/D16260 llvm-svn: 257999
* CXX_FAST_TLS calling convention: fix issue on x86-64.Manman Ren2016-01-161-2/+2
| | | | | | | | | | | | | | %RBP can't be handled explicitly. We generate the following code: pushq %rbp movq %rsp, %rbp ... movq %rbx, (%rbp) ## 8-byte Spill where %rbp will be overwritten by the spilled value. The fix is to let PEI handle %RBP. PR26136 llvm-svn: 257997
* [Cygwin] Use -femulated-tls by default since r257718 introduced the new pass.NAKAMURA Takumi2016-01-161-5/+1
| | | | | | FIXME: Add more targets to use emutls into clang/test/Driver/emulated-tls.cpp. FIXME: Add cygwin tests into llvm/test/CodeGen/X86. Working in progress. llvm-svn: 257984
* [WebAssembly] Add some more README.txt entries.Dan Gohman2016-01-161-0/+10
| | | | llvm-svn: 257969
* [X86]: Make param names in header and body match for isCalleePop.Kevin B. Smith2016-01-161-1/+1
| | | | | | Differential Revision: http://reviews.llvm.org/D16246 llvm-svn: 257965
* [WebAssembly] Don't create a needless .note.GNU-stack sectionDan Gohman2016-01-151-0/+3
| | | | | | | | | | WebAssembly's stack will never be executable by default, so it isn't necessary to declare .note.GNU-stack sections to request a non-executable stack. Differential Revision: http://reviews.llvm.org/D15969 llvm-svn: 257962
* [NVPTX] Do not emit .hidden or .protected directives as they are not allowed ↵Artem Belevich2016-01-151-0/+3
| | | | | | by PTX. llvm-svn: 257961
* CXX_FAST_TLS calling convention: fix issue on ARM.Manman Ren2016-01-151-4/+5
| | | | | | | | | | When we have a single basic block, the explicit copy-back instructions should be inserted right before the terminator. Before this fix, they were wrongly placed at the beginning of the basic block. PR26136 llvm-svn: 257930
* CXX_FAST_TLS calling convention: fix issue on AArch64.Manman Ren2016-01-151-4/+5
| | | | | | | | | | | | When we have a single basic block, the explicit copy-back instructions should be inserted right before the terminator. Before this fix, they were wrongly placed at the beginning of the basic block. I will commit fixes to other platforms as well. PR26136 llvm-svn: 257929
* CXX_FAST_TLS calling convention: fix issue on X86-64.Manman Ren2016-01-151-4/+5
| | | | | | | | | | | | When we have a single basic block, the explicit copy-back instructions should be inserted right before the terminator. Before this fix, they were wrongly placed at the beginning of the basic block. I will commit fixes to other platforms as well. PR26136 llvm-svn: 257925
* Codegen: [PPC] Silence false-positive initialization warning. NFCKyle Butt2016-01-151-2/+2
| | | | | | | | | | Some compilers don't do exhaustive switch checking. For those compilers, add an initialization to prevent un-initialized variable warnings from firing. For compilers with exhaustive switch checking, we still get a guarantee that the switch is exhaustive, and hence the initializations are redundant, and a non-functional change. llvm-svn: 257923
* Revert "[ARM] Add ARMv8-M security extension instructions to ARMv8-M ↵Reid Kleckner2016-01-158-94/+1
| | | | | | | | | | Baseline/Mainline" This reverts commit r257883. Somehow this didn't make it into r257916. llvm-svn: 257919
* # This is a combination of 2 commits.Reid Kleckner2016-01-155-115/+7
| | | | | | | | | | | | | | | | # The first commit's message is: Revert "[ARM] Add DSP build attribute and extension targeting" This reverts commit b11cc50c0b4a7c8cdb628abc50b7dc226ff583dc. # This is the 2nd commit message: Revert "[ARM] Add new system registers to ARMv8-M Baseline/Mainline" This reverts commit 837d08454e3e5beb8581951ac26b22fa07df3cd5. llvm-svn: 257916
* [Hexagon] Generate CONST64 when optimizing for size in copy-to-combineKrzysztof Parzyszek2016-01-151-11/+64
| | | | llvm-svn: 257891
* [Hexagon] Handle DBG_VALUE instructions in copy-to-combineKrzysztof Parzyszek2016-01-151-7/+49
| | | | llvm-svn: 257890
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