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* Change LegalFPImmediates to use APFloat.Dale Johannesen2007-08-303-9/+9
| | | | | | | | | Add APFloat interfaces to ConstantFP, SelectionDAG. Fix integer bit in double->APFloat conversion. Convert LegalizeDAG to use APFloat interface in ConstantFPSDNode uses. llvm-svn: 41587
* Move getX86RegNum into X86RegisterInfo and use itDuncan Sands2007-08-296-88/+80
| | | | | | | | in the trampoline lowering. Lookup the jump and mov opcodes for the trampoline rather than hard coding them. llvm-svn: 41577
* Added method to get Mips register numbersBruno Cardoso Lopes2007-08-283-61/+113
| | | | | | | Changed the stack frame layout, StackGrowsUp fits better to Mips strange stack. Stack offset calculation bug fixed! llvm-svn: 41529
* Changed stack allocation On LowerFORMAL_ARGUMENTS.Bruno Cardoso Lopes2007-08-281-20/+29
| | | | | | | Added comments about new stack allocation. Expand SelectCC for i32 results llvm-svn: 41527
* Mask directive completed with CalleeSave infoBruno Cardoso Lopes2007-08-282-73/+111
| | | | | | Comments for Mips directives added. llvm-svn: 41526
* Added methods to record SPOffsets from LowerFORMAL_ARGUMENTSBruno Cardoso Lopes2007-08-281-3/+53
| | | | llvm-svn: 41525
* Add a comment about using libc memset/memcpy or generating inline code.Rafael Espindola2007-08-271-2/+5
| | | | llvm-svn: 41502
* call libc memcpy/memset if array size is bigger then threshold.Rafael Espindola2007-08-271-4/+4
| | | | | | | Coping 100MB array (after a warmup) shows that glibc 2.6.1 implementation on x86-64 (core 2) is 30% faster (from 0.270917s to 0.188079s) llvm-svn: 41479
* rename isOperandValidForConstraint to LowerAsmOperandForConstraint, Chris Lattner2007-08-254-36/+66
| | | | | | changing the interface to allow for future changes. llvm-svn: 41384
* Disable EH generation until PPC works 100%.Chris Lattner2007-08-241-1/+1
| | | | llvm-svn: 41360
* add a noteChris Lattner2007-08-241-0/+14
| | | | llvm-svn: 41359
* add some notes on really poor codegen.Chris Lattner2007-08-231-0/+44
| | | | llvm-svn: 41319
* new exampleChris Lattner2007-08-231-0/+17
| | | | llvm-svn: 41318
* Add the PCSymbol for Darwin x86 platforms.Bill Wendling2007-08-221-0/+1
| | | | llvm-svn: 41284
* InlineAsm asm support for integer registers addedBruno Cardoso Lopes2007-08-212-0/+81
| | | | llvm-svn: 41225
* Instruction Itinerary attribution fixedBruno Cardoso Lopes2007-08-211-0/+1
| | | | llvm-svn: 41224
* Use only 1 knob to enable exceptions on Darwin :). Anton Korobeynikov2007-08-211-0/+8
| | | | llvm-svn: 41208
* Partial implementation of calling functions with byval arguments:Rafael Espindola2007-08-201-1/+21
| | | | | | | *) The needed information is propagated to the DAG *) The X86-64 backend detects it and aborts llvm-svn: 41179
* add a noteChris Lattner2007-08-201-0/+18
| | | | llvm-svn: 41178
* MipsHi now has ouput flagBruno Cardoso Lopes2007-08-181-91/+185
| | | | | | | | | | | | MipsAdd SDNode created to add support to an Add opcode which supports input flag Added an instruction itinerary to all instruction classes Added branches with zero cond codes Now call clobbers all non-callee saved registers Call w/ register support added Added DelaySlot to branch and load instructions Added patterns to handle all setcc, brcond/setcc and MipsAdd instructions llvm-svn: 41161
* Fixed stack frame addressing bugBruno Cardoso Lopes2007-08-181-8/+8
| | | | llvm-svn: 41160
* support for Schedule included on Mips.tdBruno Cardoso Lopes2007-08-182-28/+15
| | | | llvm-svn: 41159
* Removed LowerRETURADDR, fixed small bug into LowerRET, LowerGlobalAddressBruno Cardoso Lopes2007-08-182-17/+11
| | | | | | fixed to generate instructions (add, lui) glued! llvm-svn: 41158
* Couple of small changes. Delay Slot handle header declared. Bruno Cardoso Lopes2007-08-182-2/+3
| | | | | | Newline added after macros at function init on generated asm! llvm-svn: 41157
* Added InstrItinClass support for instruction formatsBruno Cardoso Lopes2007-08-181-9/+10
| | | | llvm-svn: 41156
* Branch Analysis and InsertNoop inserted into header filesBruno Cardoso Lopes2007-08-181-2/+36
| | | | llvm-svn: 41155
* createMipsDelaySlotFillerPass added to mips codegen runtime Bruno Cardoso Lopes2007-08-181-2/+2
| | | | llvm-svn: 41154
* Added Branch Analysis support Bruno Cardoso Lopes2007-08-181-5/+234
| | | | | | Added InsertNoop support llvm-svn: 41153
* LowerRETURNADDR removed since it was wrong and does not have utility yet!Bruno Cardoso Lopes2007-08-181-2/+3
| | | | | | MipsAdd opcode added llvm-svn: 41152
* InstrItineraryData support on added.Bruno Cardoso Lopes2007-08-181-2/+8
| | | | | | Added Mips3 ISA feature (needed when supporting R4000 machines) llvm-svn: 41151
* A Pass to insert Nops on intructions with DelaySlotBruno Cardoso Lopes2007-08-181-0/+77
| | | | llvm-svn: 41150
* Mips generic fallback instruction schedule support!Bruno Cardoso Lopes2007-08-181-0/+63
| | | | llvm-svn: 41149
* Move ReturnAddrIndex variable to X86MachineFunctionInfo structure. This fixedAnton Korobeynikov2007-08-153-14/+24
| | | | | | hard to catch bugs with retaddr lowering llvm-svn: 41104
* add a note.Chris Lattner2007-08-151-0/+3
| | | | llvm-svn: 41103
* Fix a typo pointd out by Maarten ter Huurne.Evan Cheng2007-08-131-1/+1
| | | | llvm-svn: 41059
* When x86 addresses matching exceeds its recursion limit, check toDan Gohman2007-08-131-6/+12
| | | | | | | see if the base register is already occupied before assuming it can be used. This fixes bogus code generation in the accompanying testcase. llvm-svn: 41049
* Fix PR1607Chris Lattner2007-08-131-3/+3
| | | | llvm-svn: 41048
* expand a noteChris Lattner2007-08-111-3/+22
| | | | llvm-svn: 41021
* With evan's explicit flag representation, hopefully we will finally beChris Lattner2007-08-111-1/+1
| | | | | | | | | able to 3-addressify away stuff like this: movl %ecx, %eax decl %eax llvm-svn: 41020
* 64-bit SSSE3 ops that use MMX registers don't require 16-byte alignment.Bill Wendling2007-08-111-6/+21
| | | | | | Make a 'memop' pattern just for them. llvm-svn: 41017
* Use subregs to improve any_extend code generation when feasible.Christopher Lamb2007-08-102-16/+33
| | | | llvm-svn: 41013
* Increase efficiency of sign_extend_inreg by using subregisters for ↵Christopher Lamb2007-08-103-49/+89
| | | | | | truncation. As the README suggests sign_extend_subreg is selected to (sext(trunc)). llvm-svn: 41010
* Edit README in light of previous LEA16 commit.Christopher Lamb2007-08-101-3/+1
| | | | llvm-svn: 41009
* Add 2-addr to 3-addr promotion code that allows 32-bit LEA to be used via ↵Christopher Lamb2007-08-101-10/+47
| | | | | | subregisters when 16-bit LEA is disabled. llvm-svn: 41007
* propagate struct size and alignment of byval arguments to the DAGRafael Espindola2007-08-101-1/+6
| | | | llvm-svn: 40986
* For kicks, I though it would be fun to use the correct opcode.Bill Wendling2007-08-101-31/+32
| | | | llvm-svn: 40985
* Adding SSSE3 intrinsics.Bill Wendling2007-08-101-17/+284
| | | | llvm-svn: 40982
* Temporarily backing out this change until we know why some dejagnu tests are ↵Evan Cheng2007-08-091-3/+2
| | | | | | failing. llvm-svn: 40973
* divb / mulb outputs to ah. Under x86-64 it's not legal to read ah if the ↵Evan Cheng2007-08-092-4/+46
| | | | | | instruction requires a rex prefix (i.e. outputs to r8b, etc.). So issue shift right by 8 on AX and then truncate it to 8 bits instead. llvm-svn: 40972
* GR16_ sub-register class should be GR8_, not GR8. That is, it should only be ↵Evan Cheng2007-08-091-3/+4
| | | | | | 8-bit registers in 32-bit mode. Ditto for GR32_. llvm-svn: 40970
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