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* AMDGPU/GlobalISel: Use and instead of BFE with inline immediateMatt Arsenault2019-07-011-6/+29
| | | | | | | Zext from s1 is the only case where this should do anything with the current legal extensions. llvm-svn: 364760
* [mips] Add missing schedinfo for MSA and ASE instructionsSimon Atanasyan2019-07-013-2/+12
| | | | llvm-svn: 364757
* [mips] Add missing schedinfo for atomic instructionsSimon Atanasyan2019-07-012-3/+22
| | | | llvm-svn: 364756
* [mips] Add missing schedinfo for ADJCALLSTACKDOWN, ADJCALLSTACKUPSimon Atanasyan2019-07-011-1/+1
| | | | llvm-svn: 364755
* [AMDGPU] Call isLoopExiting for blocks in the loop.Florian Hahn2019-07-011-2/+4
| | | | | | | | | | | | | | | | isLoopExiting should only be called for blocks in the loop. A follow up patch makes this requirement an assertion. I've updated the usage here, to only match for actual exit blocks. Previously, it would also match blocks not in the loop. Reviewers: arsenm, nhaehnle Reviewed By: nhaehnle Differential Revision: https://reviews.llvm.org/D63980 llvm-svn: 364750
* [RISCV] Add break; to the last switch caseFangrui Song2019-07-011-0/+1
| | | | | | As suggested by jrtc27 in the post-commit review of D60528. llvm-svn: 364746
* [X86] CombineShuffleWithExtract - updated description comments. NFCI.Simon Pilgrim2019-07-011-4/+4
| | | | | | CombineShuffleWithExtract no longer requires that both shuffle ops are extract_subvectors, from the same type or from the same size. llvm-svn: 364745
* [ARM] WLS/LE Code GenerationSam Parker2019-07-017-28/+162
| | | | | | | | | | | | | | | | | Backend changes to enable WLS/LE low-overhead loops for armv8.1-m: 1) Use TTI to communicate to the HardwareLoop pass that we should try to generate intrinsics that guard the loop entry, as well as setting the loop trip count. 2) Lower the BRCOND that uses said intrinsic to an Arm specific node: ARMWLS. 3) ISelDAGToDAG the node to a new pseudo instruction: t2WhileLoopStart. 4) Add support in ArmLowOverheadLoops to handle the new pseudo instruction. Differential Revision: https://reviews.llvm.org/D63816 llvm-svn: 364733
* [X86] Improve the type checking fast-isel handling of vector bitcasts.Craig Topper2019-07-011-13/+8
| | | | | | | | | | | | | | | We had a bunch of vector size legality checks for the source type based on feature flags, but we didn't check the destination type at all beyond ensuring that it was a "simple" type. But this allowed the destination to be i128 which isn't legal. This commit changes the code to use TLI's isTypeLegal logic in place of the all the subtarget checks. Then additionally checks that the source and dest are vectors. Fixes 42452 llvm-svn: 364729
* [X86] Add a DAG combine to replace vector loads feeding a v4i32->v2f64 ↵Craig Topper2019-07-012-0/+44
| | | | | | | | | | | | | | CVTSI2FP/CVTUI2FP node with a vzload. But only when the load isn't volatile. This improves load folding during isel where we only have vzload and scalar_to_vector+load patterns. We can't have full vector load isel patterns for the same volatile load issue. Also add some missing masked cvtsi2fp/cvtui2fp with vzload patterns. llvm-svn: 364728
* [X86] Add MOVHPDrm/MOVLPDrm patterns that use VZEXT_LOAD.Craig Topper2019-07-012-0/+18
| | | | | | | | | We already had patterns that used scalar_to_vector+load. But we can also have a vzload. Found while investigating combining scalar_to_vector+load to vzload. llvm-svn: 364726
* Cleanup: llvm::bsearch -> llvm::partition_point after r364719Fangrui Song2019-06-301-2/+2
| | | | llvm-svn: 364720
* [X86] Custom lower AVX masked loads to masked load and vselect instead of ↵Craig Topper2019-06-302-16/+29
| | | | | | | | | | | | selecting a maskmov+vblend during isel. AVX masked loads only support 0 as the value for masked off elements. So we need an extra blend to support other values. Previously we expanded the masked load to two instructions with isel patterns. With this patch we now insert the vselect during lowering and it will be separately selected as a blend. llvm-svn: 364718
* AMDGPU/GlobalISel: RegBankSelect for update.dppMatt Arsenault2019-06-291-0/+1
| | | | llvm-svn: 364701
* AMDGPU/GlobalISel: RegBankSelect for atomic.inc/atomic.decMatt Arsenault2019-06-291-0/+2
| | | | llvm-svn: 364699
* AMDGPU/GlobalISel: RegBankSelect for some DS intrinsicsMatt Arsenault2019-06-291-1/+17
| | | | llvm-svn: 364698
* AMDGPU/GlobalISel: RegBankSelect for some easy intrinsicsMatt Arsenault2019-06-291-1/+48
| | | | llvm-svn: 364697
* AMDGPU/GlobalISel: RegBankSelect for icmp/fcmp intrinsicsMatt Arsenault2019-06-291-0/+12
| | | | llvm-svn: 364696
* AMDGPU/GlobalISel: RegBankSelect for amdgcn.div.fmasMatt Arsenault2019-06-291-0/+1
| | | | llvm-svn: 364695
* AMDGPU/GlobalISel: RegBankSelect for some simple leaf intrinsicsMatt Arsenault2019-06-291-1/+11
| | | | llvm-svn: 364694
* [WebAssembly] Assembler: support .int16/32/64 directives.Wouter van Oortmerssen2019-06-281-6/+11
| | | | | | | | | | | | Reviewers: sbc100 Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63959 llvm-svn: 364689
* [x86] remove stale comment about cmov; NFCSanjay Patel2019-06-281-2/+1
| | | | | | | The cmov node used to sometimes return a glue result (and that's what 'flag' meant in this context), but that was removed with D38664. llvm-svn: 364687
* [WebAssembly] Assembler: Allow offsets and p2align in symbol load.Wouter van Oortmerssen2019-06-281-6/+8
| | | | | | | | | | | | Reviewers: sbc100 Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63951 llvm-svn: 364682
* [WebAssembly] Assembler: Improve section parsing.Wouter van Oortmerssen2019-06-281-0/+4
| | | | | | | | | | | | Reviewers: sbc100 Subscribers: dschuff, jgravelle-google, aheejin, sunfish, llvm-commits Tags: #llvm Differential Revision: https://reviews.llvm.org/D63947 llvm-svn: 364681
* Default to Secure PLT on PPC for musl libc.Brad Smith2019-06-281-1/+2
| | | | | | This matches the default settings of clang. llvm-svn: 364675
* [X86] CombineShuffleWithExtract - recurse through EXTRACT_SUBVECTOR chainSimon Pilgrim2019-06-281-9/+9
| | | | llvm-svn: 364667
* [AMDGPU][MC] Fix 2 for sanitizer failure in 364645Dmitry Preobrazhensky2019-06-282-6/+6
| | | | llvm-svn: 364656
* [ARM] Add support for the MVE long shift instructionsSam Tebbs2019-06-284-7/+85
| | | | | | | | | | | | MVE adds the lsll, lsrl and asrl instructions, which perform a shift on a 64 bit value separated into two 32 bit registers. The Expand64BitShift function is modified to accept ISD::SHL, ISD::SRL and ISD::SRA and convert it into the appropriate opcode in ARMISD. An SHL is converted into an lsll, an SRL is converted into an lsrl for the immediate form and a negation and lsll for the register form, and SRA is converted into an asrl. test/CodeGen/ARM/shift_parts.ll is added to test the logic of emitting these instructions. Differential Revision: https://reviews.llvm.org/D63430 llvm-svn: 364654
* [AMDGPU][MC] Fix for sanitizer failure in 364645Dmitry Preobrazhensky2019-06-281-4/+10
| | | | llvm-svn: 364651
* [AMDGPU][MC] Enabled constant expressions as operands of sendmsgDmitry Preobrazhensky2019-06-285-210/+266
| | | | | | | | | | See bug 40820: https://bugs.llvm.org/show_bug.cgi?id=40820 Reviewers: artem.tamazov, arsenm Differential Revision: https://reviews.llvm.org/D62735 llvm-svn: 364645
* [X86] CombineShuffleWithExtract - only require 1 source to be EXTRACT_SUBVECTORSimon Pilgrim2019-06-281-8/+16
| | | | | | | | We were requiring that both shuffle operands were EXTRACT_SUBVECTORs, but we can relax this to only require one of them to be. Also, we shouldn't bother attempting this if both operands are from the lowest subvector (or not EXTRACT_SUBVECTOR at all). llvm-svn: 364644
* [ARM] Add MVE mul patternsDavid Green2019-06-281-0/+16
| | | | | | | | | This simply adds integer and floating point VMUL patterns for MVE, same as we have add and sub. Differential Revision: https://reviews.llvm.org/D63866 llvm-svn: 364643
* [ARM] Mark math routines as non-legal for MVEDavid Green2019-06-281-0/+9
| | | | | | | | | This adds handling and tests for a number of floating point math routines, which have no MVE instructions. Differential Revision: https://reviews.llvm.org/D63725 llvm-svn: 364641
* [ARM] MVE patterns for VABS and VNEGDavid Green2019-06-281-0/+14
| | | | | | | | This simply adds the required patterns for fp neg and abs. Differential Revision: https://reviews.llvm.org/D63861 llvm-svn: 364640
* [ARM] Widening loads and narrowing storesDavid Green2019-06-283-4/+58
| | | | | | | | | | | | MVE has instructions to widen as it loads, and narrow as it stores. This adds the required patterns and legalisation to make them work including specifying that they are legal, patterns to select them and test changes. Patch by David Sherwood. Differential Revision: https://reviews.llvm.org/D63839 llvm-svn: 364636
* [ARM] Fix integer UB in MVE load/store immediate handling.Simon Tatham2019-06-282-6/+9
| | | | llvm-svn: 364635
* [ARM] MVE loads and storesDavid Green2019-06-282-11/+52
| | | | | | | | | | | | | | | This fills in the gaps for basic MVE loads and stores, allowing unaligned access and adding far too many tests. These will become important as narrowing/expanding and pre/post inc are added. Big endian might still not be handled very well, because we have not yet added bitcasts (and I'm not sure how we want it to work yet). I've included the alignment code anyway which maps with our current patterns. We plan to return to that later. Code written by Simon Tatham, with additional tests from Me and Mikhail Maltsev. Differential Revision: https://reviews.llvm.org/D63838 llvm-svn: 364633
* [AVR] Don't look for the TargetFrameLowering in the FrameLowering implementationDylan McKay2019-06-281-1/+1
| | | | | | c.f. r364349 llvm-svn: 364632
* [ARM] Mark div and rem as expand for MVEDavid Green2019-06-281-0/+12
| | | | | | | | | We don't have vector operations for these, so they need to be expanded for both integer and float. Differential Revision: https://reviews.llvm.org/D63595 llvm-svn: 364631
* [ARM] Select MVE fp add and subDavid Green2019-06-281-0/+14
| | | | | | | | | | | The same as integer arithmetic, we can add simple floating point MVE addition and subtraction patterns. Initial code by David Sherwood Differential Revision: https://reviews.llvm.org/D63257 llvm-svn: 364629
* [ARM] Select MVE add and subDavid Green2019-06-281-0/+18
| | | | | | | | | | | This adds the first few patterns for MVE code generation, adding simple integer add and sub patterns. Initial code by David Sherwood Differential Revision: https://reviews.llvm.org/D63255 llvm-svn: 364627
* [ARM] MVE vector shufflesDavid Green2019-06-285-183/+355
| | | | | | | | | | | | | | | | | | This patch adds necessary shuffle vector and buildvector support for ARM MVE. It essentially adds support for VDUP, VREVs and some VMOVs, which are often required by other code (like upcoming patches). This mostly uses the same code from Neon that already generated NEONvdup/NEONvduplane/NEONvrev's. These have been renamed to ARMvdup/etc and moved to ARMInstrInfo as they are common to both architectures. Most of the selection code seems to be applicable to both, but NEON does have some more instructions making some parts specific. Most code originally by David Sherwood. Differential Revision: https://reviews.llvm.org/D63567 llvm-svn: 364626
* [X86] Connect the output chain properly when combining vzext_movl+load into ↵Craig Topper2019-06-281-1/+1
| | | | | | vzext_load. llvm-svn: 364625
* [X86] Remove some duplicate patterns that already exist as part of their ↵Craig Topper2019-06-281-5/+1
| | | | | | instruction definition. NFC llvm-svn: 364623
* [NFC][PowerPC] Move XS*QP series instruction apart from XS*QPO series in ↵Zi Xuan Wu2019-06-281-33/+33
| | | | | | position of td file llvm-svn: 364620
* [AMDGPU] Packed thread ids in function call ABIStanislav Mekhanoshin2019-06-284-22/+132
| | | | | | Differential Revision: https://reviews.llvm.org/D63851 llvm-svn: 364619
* [PowerPC][NFC] Use `|=` to update `Simplified` flagKai Luo2019-06-281-1/+1
| | | | llvm-svn: 364617
* AMDGPU/GlobalISel: Convert to using RegisterMatt Arsenault2019-06-284-44/+44
| | | | llvm-svn: 364616
* [x86] prevent crashing from select narrowing with AVX512Sanjay Patel2019-06-271-0/+9
| | | | llvm-svn: 364585
* [PowerPC][NFC] Remove unused (and unsupported) fusion feature bits.Jinsong Ji2019-06-273-7/+1
| | | | | | | | | | | | | | | FeatureFusion bits was first introduced in https://reviews.llvm.org/rL253724. for add/load integer fusion for P8. The only use of `hasFusion` was https://reviews.llvm.org/rL255319. However, this was removed later in https://reviews.llvm.org/rL280440. So, there is NO any reference to fusion in code now. Leaving it there is misleading and confusing, so remove it for now. We can alwasy add back if we ever support fusion in the future. llvm-svn: 364581
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