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* Merge x86 HasOpSizePrefix/HasOpSize16Prefix into a 2-bit OpSize field with 0 ↵Craig Topper2014-02-0213-499/+498
| | | | | | meaning no 0x66 prefix in any mode. Rename Opsize16->OpSize32 and OpSize->OpSize16. The classes now refer to their operand size rather than the mode in which they need a 0x66 prefix. Hopefully can merge REX_W into this as OpSize64. llvm-svn: 200626
* Merge HasVEXPrefix/HasEVEXPrefix/HasXOPPrefix into a 2-bit 'encoding' field ↵Craig Topper2014-02-026-143/+171
| | | | | | in TSFlags. llvm-svn: 200624
* Replace PPC instruction-size code with MCInstrDesc getSizeHal Finkel2014-02-022-20/+11
| | | | | | | | | | As part of the cleanup done to enable the disassembler, the PPC instructions now have a valid Size description field. This can now be used to replace some custom logic in a few places to compute instruction sizes. Patch by David Wiberg! llvm-svn: 200623
* R600/SI: Fix insertelement with dynamic indices.Matt Arsenault2014-02-021-7/+17
| | | | | | | | This didn't work for any integer vectors, and didn't work with some sizes of float vectors. This should now work with all sizes of float and i32 vectors. llvm-svn: 200619
* [Sparc] Set %o7 as the return address register instead of %i7 in ↵Venkatraman Govindaraju2014-02-012-4/+23
| | | | | | MCRegisterInfo. Also, add CFI instructions to initialize the frame correctly. llvm-svn: 200617
* ARMTTI: We don't have 16 allocatable scalar registersArnold Schwaighofer2014-02-011-1/+1
| | | | | | | This caused an regression on libquantum after enabling the new loop vectorizer unroll heuristics. llvm-svn: 200616
* Simplify some x86 format classes and remove some ambiguities in their ↵Craig Topper2014-02-013-43/+46
| | | | | | application. llvm-svn: 200608
* Implement inalloca codegen for x86 with the new inalloca designReid Kleckner2014-01-312-6/+27
| | | | | | | | | | | | | | | | Calls with inalloca are lowered by skipping all stores for arguments passed in memory and the initial stack adjustment to allocate argument memory. Now the frontend is responsible for the memory layout, and the backend doesn't have to do any work. As a result these changes are pretty minimal. Reviewers: echristo Differential Revision: http://llvm-reviews.chandlerc.com/D2637 llvm-svn: 200596
* Don't put non-static allocas in the static alloca mapReid Kleckner2014-01-311-0/+1
| | | | | | | | Allocas marked inalloca are never static, but we were trying to put them into the static alloca map if they were in the entry block. Also add an assertion in x86 fastisel. llvm-svn: 200593
* Remove another hasRawTextSupport.Rafael Espindola2014-01-3110-146/+45
| | | | | | | | | To remove this one simply move the end of file logic from the asm printer to the target mc streamer. This removes the last call to hasRawTextSupport from lib/Target. llvm-svn: 200590
* Remove the last hasRawTextSupport call from R600.Rafael Espindola2014-01-311-2/+1
| | | | | | | | There is nothing wrong with printing the disassembly section when printing text. An hypothetical assembler would then produce a .o just like our direct object emission produces. llvm-svn: 200583
* Replace another use with hasRawTextSupport+EmitRawText with emitRawComment.Rafael Espindola2014-01-311-2/+2
| | | | llvm-svn: 200582
* Use emitRawComment to avoid a call to hasRawTextSupport.Rafael Espindola2014-01-311-3/+1
| | | | llvm-svn: 200581
* Replace X86 FMA intrinsic pseduo-instructions with def pats.Lang Hames2014-01-312-34/+21
| | | | | | | | | | | It looks like these pseudos were only used for pattern matching. Def pats are the appropriate way to do that. As a bonus, these intrinsics will now have memory operands folded properly, and better FMA3 variants selected where appropriate (see r199933). <rdar://problem/15611947> llvm-svn: 200577
* x86: Rename NumBytesForCalleeToPush to ...Pop for accuracyReid Kleckner2014-01-311-5/+5
| | | | | | | If we have a callee cleanup convention, the callee is going to pop the arguments off the stack, not push them on. llvm-svn: 200566
* [ms-cxxabi] Add a new calling convention that swaps 'this' and 'sret'Reid Kleckner2014-01-312-0/+37
| | | | | | | | | | | | | | | | | | | | MSVC always places the 'this' parameter for a method first. The implicit 'sret' pointer for methods always comes second. We already implement this for __thiscall by putting sret parameters on the stack, but __cdecl methods require putting both parameters on the stack in opposite order. Using a special calling convention allows frontends to keep the sret parameter first, which avoids breaking lots of assumptions in LLVM and Clang. Fixes PR15768 with the corresponding change in Clang. Reviewers: ributzka, majnemer Differential Revision: http://llvm-reviews.chandlerc.com/D2663 llvm-svn: 200561
* [mips][msa] Add insert.d instruction.Matheus Almeida2014-01-312-0/+19
| | | | | | This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200543
* Separate x86 opcode maps and 0x66/0xf2/0xf3 prefixes from each other in the ↵Craig Topper2014-01-314-288/+215
| | | | | | TSFlags. This greatly simplifies the switch statements in the disassembler tables and the code emitters. llvm-svn: 200522
* Move REP out of the Prefix field of the X86 format. Give it its own bit. It ↵Craig Topper2014-01-314-35/+35
| | | | | | had special handling anyway and this enables a future patch. llvm-svn: 200520
* Move address override handling in X86CodeEmitter to a place where it works ↵Craig Topper2014-01-311-28/+28
| | | | | | for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode. llvm-svn: 200517
* Move address override handling in X86MCCodeEmitter to a place where it works ↵Craig Topper2014-01-311-46/+43
| | | | | | for VEX encoded instructions too. This allows 32-bit addressing to work in 64-bit mode. llvm-svn: 200516
* [Sparc] Save and restore float registers that may be used for parameter passing.Venkatraman Govindaraju2014-01-311-2/+44
| | | | llvm-svn: 200509
* [x86] Fix signed relocations for i64i32imm operandsDavid Woodhouse2014-01-305-55/+84
| | | | | | | | | These should end up (in ELF) as R_X86_64_32S relocs, not R_X86_64_32. Kill the horrid and incomplete special case and FIXME in EncodeInstruction() and set things up so it can infer the signedness from the ImmType just like it can the size and whether it's PC-relative. llvm-svn: 200495
* [AArch64] Custom lower concat_vector patterns with v4i16, v4i32, v8i8, ↵Chad Rosier2014-01-302-0/+67
| | | | | | v8i16, v16i8 types. llvm-svn: 200491
* Reenable ARM EHABI on Android.Evgeniy Stepanov2014-01-301-1/+2
| | | | | | Broken in r200388. llvm-svn: 200466
* [mips] Fix typo.Matheus Almeida2014-01-301-1/+1
| | | | llvm-svn: 200465
* Remove duplicate patternsCraig Topper2014-01-301-5/+0
| | | | llvm-svn: 200461
* Remove some AddedComplexity tags that were forcing priority for AVX over ↵Craig Topper2014-01-301-36/+36
| | | | | | SSE. Use predicates instead. llvm-svn: 200458
* Remove duplicate pattern and add predicate checks on other patterns.Craig Topper2014-01-301-1/+2
| | | | llvm-svn: 200455
* Implement SPARCv9 atomic_swap_64 with a pseudo.Jakob Stoklund Olesen2014-01-302-3/+15
| | | | | | | | The SWAP instruction only exists in a 32-bit variant, but the 64-bit atomic swap can be implemented in terms of CASX, like the other atomic rmw primitives. llvm-svn: 200453
* ARM IAS: support .object_archSaleem Abdulrasool2014-01-302-3/+59
| | | | | | | | | | The .object_arch directive indicates an alternative architecture to be specified in the object file. The directive does *not* effect the enabled feature bits for the object file generation. This is particularly useful when the code performs runtime detection and would like to indicate a lower architecture as the requirements than the actual instructions used. llvm-svn: 200451
* ARM IAS: support .movspSaleem Abdulrasool2014-01-303-6/+102
| | | | | | | | .movsp is an ARM unwinding directive that indicates to the unwinder that a register contains an offset from the current stack pointer. If the offset is unspecified, it defaults to zero. llvm-svn: 200449
* ARM: suuport .tlsdescseq directiveSaleem Abdulrasool2014-01-303-0/+49
| | | | | | | | | | | This enhances the ARMAsmParser to handle .tlsdescseq directives. This is a slightly special relocation. We must be able to generate them, but not consume them in assembly. The relocation is meant to assist the linker in generating a TLS descriptor sequence. The ELF target streamer is enhanced to append additional fixups into the current segment and that is used to emit the new R_ARM_TLS_DESCSEQ relocations. llvm-svn: 200448
* ARM: support TLS descriptor relocationsSaleem Abdulrasool2014-01-301-0/+3
| | | | | | | | Add support for tlsdesc relocations which are part of the ABI, marked as experimental. These relocations permit the linker to perform TLS reference optimizations. llvm-svn: 200447
* ARM: support tlscall relocationsSaleem Abdulrasool2014-01-302-1/+20
| | | | | | | | | | | | | | This adds support for TLS CALL relocations. TLS CALL relocations are used to indicate to the linker to generate appropriate entries to resolve TLS references via an appropriate function invocation (e.g. __tls_get_addr(PLT)). In order to accomodate the linker relaxation of the TLS access model for the references (GD/LD -> IE, IE -> LE), the relocation addend must be incomplete. This requires that the partial inplace value is also incomplete (i.e. 0). We simply avoid the offset value calculation at the time of the fixup adjustment in the ARM assembler backend. llvm-svn: 200446
* Simplify the handling of iterators in ObjectFile.Rafael Espindola2014-01-301-4/+4
| | | | | | | | | | | | None of the object file formats reported error on iterator increment. In retrospect, that is not too surprising: no object format stores symbols or sections in a linked list or other structure that requires chasing pointers. As a consequence, all error checking can be done on begin() and end(). This reduces the text segment of bin/llvm-readobj in my machine from 521233 to 518526 bytes. llvm-svn: 200442
* [X86][SchedModel] Fix typos in the definitions of the ports for Haswell.Quentin Colombet2014-01-291-6/+8
| | | | llvm-svn: 200403
* Test commitOliver Stannard2014-01-291-0/+1
| | | | llvm-svn: 200401
* [mips][msa] Add fill.d instruction.Matheus Almeida2014-01-292-1/+16
| | | | | | | This instruction is only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200400
* [mips][msa] Add copy_{u,s}.d.Matheus Almeida2014-01-293-14/+52
| | | | | | | These instructions are only available on Mips64 cores that implement the MSA ASE. llvm-svn: 200398
* Enable EHABI by defaultRenato Golin2014-01-293-5/+18
| | | | | | | | | | | | | | | | | | | | | | After all hard work to implement the EHABI and with the test-suite passing, it's time to turn it on by default and allow users to disable it as a work-around while we fix the eventual bugs that show up. This commit also remove the -arm-enable-ehabi-descriptors, since we want the tables to be printed every time the EHABI is turned on for non-Darwin ARM targets. Although MCJIT EHABI is not working yet (needs linking with the right libraries), this commit also fixes some relocations on MCJIT regarding the EH tables/lib calls, and update some tests to avoid using EH tables when none are needed. The EH tests in the test-suite that were previously disabled on ARM now pass with these changes, so a follow-up commit on the test-suite will re-enable them. llvm-svn: 200388
* [Sparc] Use %r_disp32 for pc_rel entries in FDE as well.Venkatraman Govindaraju2014-01-292-0/+16
| | | | | | This makes MCAsmInfo::getExprForFDESymbol() a virtual function and overrides it in SparcMCAsmInfo. llvm-svn: 200376
* [Sparc] Use %r_disp32 for pc_rel entries in gcc_except_table and eh_frame.Venkatraman Govindaraju2014-01-298-7/+107
| | | | | | | | Otherwise, assembler (gas) fails to assemble them with error message "operation combines symbols in different segments". This is because MC computes pc_rel entries with subtract expression between labels from different sections. llvm-svn: 200373
* [SparcV9] Use correct register class (I64RegClass) to hold the address of ↵Venkatraman Govindaraju2014-01-292-3/+4
| | | | | | _GLOBAL_OFFSET_TABLE_ in sparcv9. llvm-svn: 200368
* [AArch64 NEON] Lower SELECT_CC with vector operand.Kevin Qin2014-01-292-56/+182
| | | | | | | | When the scalar compare is between floating point and operands are vector, we custom lower SELECT_CC to use NEON SIMD compare for generating less instructions. llvm-svn: 200365
* [Sparc] Fix breakage in r200345David Woodhouse2014-01-281-9/+10
| | | | | | Oops. Don't do build tests on patches like that with --enable-targets=x86_64 llvm-svn: 200355
* Delete MCSubtargetInfo data members from target MCCodeEmitter classesDavid Woodhouse2014-01-286-107/+99
| | | | | | | | The subtarget info is explicitly passed to the EncodeInstruction method and we should use that subtarget info to influence any encoding decisions. llvm-svn: 200350
* Propagate MCSubtargetInfo through TableGen's getBinaryCodeForInstr()David Woodhouse2014-01-289-310/+545
| | | | llvm-svn: 200349
* Explictly pass MCSubtargetInfo to MCCodeEmitter::EncodeInstruction()David Woodhouse2014-01-2810-18/+36
| | | | llvm-svn: 200348
* Change MCStreamer EmitInstruction interface to take subtarget infoDavid Woodhouse2014-01-2821-147/+156
| | | | llvm-svn: 200345
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