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* [mips] Refactor calls to setCanHaveModuleDir.Toma Tabacu2014-08-132-133/+55
| | | | | | | | | | | | | | | | | Summary: Moved some calls to setCanHaveModuleDir to the MipsTargetStreamer base class and removed the resulting empty functions from the MipsTargetELFStreamer class. Also fixed a missing call to setCanHaveModuleDir in MipsTargetELFStreamer::emitDirectiveSetMicroMips. Reviewers: dsanders Reviewed By: dsanders Subscribers: tomatabacu Differential Revision: http://reviews.llvm.org/D4781 llvm-svn: 215542
* Silence a -Wparenthesis warning with these asserts. NFC.Aaron Ballman2014-08-131-2/+2
| | | | llvm-svn: 215537
* [SKX] Extended non-temporal load/store instructions for AVX512VL subsets.Robert Khasanov2014-08-133-34/+67
| | | | | | | | | Added avx512_movnt_vl multiclass for handling 256/128-bit forms of instruction. Added encoding and lowering tests. Reviewed by Elena Demikhovsky <elena.demikhovsky@intel.com> llvm-svn: 215536
* Re-commit: [mips] Implement .ent, .end, .frame, .mask and .fmask.Daniel Sanders2014-08-133-22/+263
| | | | | | | | | | | Patch by Matheus Almeida and Toma Tabacu The lld test failure on the previous attempt to commit was caused by the addition of the .pdr section causing the offsets it was checking to change. This has been fixed by removing the .ent/.end directives from that test since they weren't really needed. llvm-svn: 215535
* AVX-512: Fixed a bug in shufflevector lowering.Elena Demikhovsky2014-08-131-1/+2
| | | | | | | PALIGNR instruction does not exist in AVX-512F set. Added a test. llvm-svn: 215526
* [NVPTX] Remove MemIntrinsicSDNode/MemSDNode duplicate checkingHal Finkel2014-08-131-7/+0
| | | | | | | | | | | As of r214452, isa<MemSDNode> will return true for nodes for which isa<MemIntrinsicSDNode> will return true (classof now respects the actual class hierarchy). So we no longer need to check for both MemIntrinsicSDNode and MemSDNode separately. No functionality change intended. llvm-svn: 215523
* [x86] Rewrite a core part of the new vector shuffle lowering to handleChandler Carruth2014-08-131-22/+122
| | | | | | | | | | | | | | | | | | | | one pesky test case correctly. This test case caused the old code to infloop occilating between solving the low-half and the high-half. The 'side balancing' part of single-input v8 shuffle lowering didn't handle the one pattern which can cause it to occilate. Fortunately the fuzz testing found this case. Unfortuately it was *terrible* to handle. I'm really sorry for the amount and density of the code here, I'd love suggestions on how to simplify it. I feel like there *must* be a simpler form here, but after a lot of days I've not found it. This is the only one I've found that even works. I've added the one pesky test case along with some nice comments explaining the core problem that we have to solve here. So far this has survived approximately 32k test cases. More strenuous fuzzing commencing. llvm-svn: 215519
* [PowerPC] Implement PPCTargetLowering::getTgtMemIntrinsicHal Finkel2014-08-132-0/+80
| | | | | | | | | | | | | | | | | This implements PPCTargetLowering::getTgtMemIntrinsic for Altivec load/store intrinsics. As with the construction of the MachineMemOperands for the intrinsic calls used for unaligned load/store lowering, the only slight complication is that we need to represent a larger memory range than the loaded/stored value-type size (because the address is rounded down to an aligned address, and we need to conservatively represent the entire possible range of the actual access). This required adding an extra size field to TargetLowering::IntrinsicInfo, and this was done in a way that required no modifications to other targets (the size defaults to the store size of the provided memory data type). This fixes test/CodeGen/PowerPC/unal-altivec-wint.ll (so it can be un-XFAILed). llvm-svn: 215512
* [AVX512] Handle valign masking intrinsic via C++ loweringAdam Nemet2014-08-122-16/+16
| | | | | | | | | | | | | | I think that this will scale better in most cases than adding a Pat<> for each mapping from the intrinsic DAG to the intruction (i.e. rri, rrik, rrikz). We can just lower to the SDNode and have the resulting DAG be matches by the DAG patterns. Alternatively (long term), we could keep the Pat<>s but generate them via the new AVX512_masking multiclass. The difficulty is that in order to formulate that we would have to concatenate DAGs. Currently this is only supported if the operators of the input DAGs are identical. llvm-svn: 215473
* R600: Use optimized 24bit path in udivremJan Vesely2014-08-122-18/+39
| | | | | | | | | v2: drop enum keyword use correct extension mode don't bother computing the sign in unsinged case Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 215462
* R600: Remove unused code.Jan Vesely2014-08-122-174/+0
| | | | | Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 215461
* R600: Use i24 optimized path for SREMJan Vesely2014-08-122-8/+28
| | | | | | | | | v2: add tests rename LowerSDIV24 to LowerSDIVREM24 handle the rem part in this function Signed-off-by: Jan Vesely <jan.vesely@rutgers.edu> llvm-svn: 215460
* fixed typosSanjay Patel2014-08-121-5/+5
| | | | llvm-svn: 215451
* Reverted my "Testing commit access" commit.Toma Tabacu2014-08-121-0/+1
| | | | llvm-svn: 215441
* Testing commit access.Toma Tabacu2014-08-121-1/+0
| | | | llvm-svn: 215440
* [MachineCombiner] Fix for ICE bug 20598Gerolf Hoflehner2014-08-121-1/+2
| | | | | | | | | | | | | | | | | | The combiner ignored DBG nodes when checking the uses of a virtual register. It combined a sequence like %vreg1 = madd %vreg2, %vreg3,... DBG_VALUE (%vreg1 ...) %vreg4 = add %vreg1,... to %vreg4 = madd %vreg2, %vreg3 leaving behind a dangling DBG_VALUE with a definition. This triggered an assertion in the MachineTraceMetrics.cpp module. llvm-svn: 215431
* IR: Print a newline when dumping TypesJustin Bogner2014-08-121-1/+1
| | | | | | | | | | | | Type::dump() doesn't print a newline, which makes for a poor experience in a debugger. This looks like it was an ommission considering Value::dump() two lines above, so I've changed Type to add a newline as well. Of the two in-tree callers, one added a newline anyway, and I've updated the other one to use Type::print instead. llvm-svn: 215421
* R600/SIInstrInfo.cpp: Suppress an warning. [-Wunused-variable]NAKAMURA Takumi2014-08-111-0/+1
| | | | llvm-svn: 215406
* [ARM] Mark VMOVDRR with the RegSequence property and implement the relatedQuentin Colombet2014-08-113-0/+46
| | | | | | | | | | | | | target hook. This patch teaches the compiler that: dX = VMOVDRR rY, rZ is the same as: dX = REG_SEQUENCE rY, ssub_0, rZ, ssub_1 <rdar://problem/12702965> llvm-svn: 215404
* Add missing closing namespace comment.Jim Grosbach2014-08-111-1/+1
| | | | llvm-svn: 215402
* AArch64: Tidy up a few comments.Jim Grosbach2014-08-111-2/+2
| | | | | | Have the comments match the actual parameter names. Found via clang-tidy. llvm-svn: 215401
* R600/SI: Add a ComplexPattern for selecting MUBUF _OFFSET variantTom Stellard2014-08-114-155/+289
| | | | | | | This saves us from having to copy a 64-bit 0 value into VGPRs for BUFFER_* instruction which only have a 12-bit immediate offset. llvm-svn: 215399
* R600/SI: Add an _OFFEN variant MUBUF_STORE_* and use it for scratch writesTom Stellard2014-08-112-23/+34
| | | | llvm-svn: 215398
* R600/SI: Clear lds bit on MUBUF instructions used for private storesTom Stellard2014-08-111-0/+1
| | | | | | | | This bit was left uninitialized, which was causing some random failures of piglit tests. NOTE: This is a candidate for the 3.5 branch. llvm-svn: 215396
* [AArch64] Fix registerAllocator assigns same register for base and wback inQuentin Colombet2014-08-111-7/+6
| | | | | | | | pre/post-index load and store. Patch by Steven Wu <stevenwu@apple.com> llvm-svn: 215390
* ARM: try harder to detect non-IT eligible instructionsSaleem Abdulrasool2014-08-111-7/+32
| | | | | | | | | | | | | | | | | | | For many Thumb-1 register register instructions, setting the CPSR is not permitted inside an IT block. We would not correctly flag those instructions. The previous change to identify this scenario was insufficient as it did not actually catch all the instances. The current list is formed by manual inspection of the ARMv6M ARM. The change to the Thumb2 IT block test is due to the fact that the new more stringent checking of the MIs results in the If Conversion pass being prevented from executing (since not all the instructions in the BB are predicable). This results in code gen changes. Thanks to Tim Northover for pointing out that the previous patch was insufficient and hinting that the use of the v6M ARM would be much easier to use than the v7 or v8! llvm-svn: 215382
* Fix typos:Sylvestre Ledru2014-08-115-5/+5
| | | | | | | * libaries => libraries * avaiable => available llvm-svn: 215366
* Revert r215359 - [mips] Implement .ent, .end, .frame, .mask and .fmask ↵Daniel Sanders2014-08-113-263/+22
| | | | | | | | assembler directives It seems to cause an lld test (elf/Mips/hilo16-3.test) to fail. Reverted while we investigate. llvm-svn: 215361
* [mips] Implement .ent, .end, .frame, .mask and .fmask assembler directivesDaniel Sanders2014-08-113-22/+263
| | | | | | | | Patch by Matheus Almeida and Toma Tabacu Differential Revision: http://reviews.llvm.org/D4179 llvm-svn: 215359
* AVX-512: added a missing bitcast from v16f32 to v16i32Elena Demikhovsky2014-08-111-0/+1
| | | | llvm-svn: 215351
* ARM: __gnu_h2f_ieee and __gnu_f2h_ieee always use the soft-float calling ↵Oliver Stannard2014-08-111-0/+13
| | | | | | | | | | | | convention By default, LLVM uses the "C" calling convention for all runtime library functions. The half-precision FP conversion functions use the soft-float calling convention, and are needed for some targets which use the hard-float convention by default, so must have their calling convention explicitly set. llvm-svn: 215348
* Increase the size of these SmallVectors in X86ISelLowering.cpp.Hans Wennborg2014-08-111-3/+3
| | | | | | In a Clang bootstrap, their sizes were always 12, 16 and 16, respectively. llvm-svn: 215336
* ARM: correct isPredicable for MULS in ThHUMB modeSaleem Abdulrasool2014-08-101-0/+14
| | | | | | | | | | | | | | | | | | The ARM ARM states that CPSR may not be updated by a MUL in thumb mode. Due to an ordering of Thumb 2 Size Reduction and If Conversion, we would end up generating a THUMB MULS inside an IT block. The If Conversion pass uses the TTI isPredicable method to ensure that it can transform a Basic Block. However, because we only check for IT handling on Thumb2 functions, we may miss some cases. Even then, it only validates that the CPSR is not *live* rather than it is not accessed. This corrects the handling for that particular case since the same restriction does not hold on the vast majority of the instructions. This does prevent the IfConversion optimization from kicking in in certain cases, but generating correct code is more valuable. Addresses PR20555. llvm-svn: 215328
* @l and friends adjust their value depending the context used in.Joerg Sonnenberger2014-08-104-36/+142
| | | | | | | For ori, they are unsigned, for addi, signed. Create a new target expression type to handle this and evaluate Fixups accordingly. llvm-svn: 215315
* If available, pass down the Fixup object to EvaluateAsRelocatable.Joerg Sonnenberger2014-08-1012-22/+29
| | | | | | | At least on PowerPC, the interpretation of certain modifiers depends on the context they appear in. llvm-svn: 215310
* fixed typosSanjay Patel2014-08-091-2/+2
| | | | llvm-svn: 215299
* Resolving some type truncation warnings in MSVC (enum to bool in this case). ↵Aaron Ballman2014-08-091-3/+3
| | | | | | No functional changes intended. llvm-svn: 215293
* Allow the third argument for the subi family to be an expression.Joerg Sonnenberger2014-08-091-8/+27
| | | | llvm-svn: 215286
* Use the full form of dccci and iccci from the early PPC 405 documents,Joerg Sonnenberger2014-08-091-15/+9
| | | | | | | since the operands are actually used on those cores. Provide aliases for the only documented case in the newer Power ISA speec. llvm-svn: 215282
* Initialize PPC DataLayout based on the Triple only.Eric Christopher2014-08-092-11/+12
| | | | llvm-svn: 215281
* Remove extraneous 64-bit argument to the PPC TargetMachine constructorEric Christopher2014-08-094-11/+13
| | | | | | and update initialization. llvm-svn: 215280
* Initialize X86 DataLayout based on the Triple only.Eric Christopher2014-08-092-14/+17
| | | | llvm-svn: 215279
* R600: Disable FP exceptions.Matt Arsenault2014-08-091-0/+5
| | | | llvm-svn: 215277
* Move some X86 subtarget configuration onto the subtarget that's beingEric Christopher2014-08-092-21/+22
| | | | | | created. llvm-svn: 215271
* R600/SI: Custom lower CONCAT_VECTORSTom Stellard2014-08-091-1/+3
| | | | | | | This will lower them using register copies rather than loads and stores to the stack. llvm-svn: 215270
* [FastISel][X86] Silence -Wenum-compare warningRui Ueyama2014-08-081-2/+6
| | | | llvm-svn: 215253
* Allow large immediates for branch instructions in 32bit mode.Joerg Sonnenberger2014-08-081-3/+17
| | | | llvm-svn: 215240
* Provide an implementation of getNoopForMachoTarget for PPC, otherwiseJoerg Sonnenberger2014-08-082-0/+7
| | | | | | empty functions will assert in the MC object writer. llvm-svn: 215238
* [FastISel][X86] Fix INC/DEC optimization (r215230)Juergen Ributzka2014-08-081-1/+1
| | | | | | | | I accidentally also used INC/DEC for unsigned arithmetic which doesn't work, because INC/DEC don't set the required flag which is used for the overflow check. llvm-svn: 215237
* AArch64: avoid deleting the current iterator in a loop.Tim Northover2014-08-081-3/+4
| | | | | | | | std::map invalidates the iterator to any element that gets deleted, which means we can't increment it correctly afterwards. This was causing Darwin test failures. llvm-svn: 215233
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