| Commit message (Collapse) | Author | Age | Files | Lines |
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ISD::VECTOR_SHUFFLE now stores an array of integers representing the shuffle
mask internal to the node, rather than taking a BUILD_VECTOR of ConstantSDNodes
as the shuffle mask. A value of -1 represents UNDEF.
In addition to eliminating the creation of illegal BUILD_VECTORS just to
represent shuffle masks, we are better about canonicalizing the shuffle mask,
resulting in substantially better code for some classes of shuffles.
A clean up of x86 shuffle code, and some canonicalizing in DAGCombiner is next.
llvm-svn: 69952
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llvm-svn: 69934
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an insn from beginnin to find out the banksel operand.
llvm-svn: 69883
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memory operand tuples. This doesn't ever come up in normal
code however.
llvm-svn: 69848
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The address of data frame for function can be obtained by subtracting 2 from the function begin label.
llvm-svn: 69801
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Spotted by gcc-4.5.
llvm-svn: 69673
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This fixes PR4002.
llvm-svn: 69672
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llvm-svn: 69665
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This makes the extra copyRegToReg calls in ScheduleDAGSDNodesEmit.cpp
unnecessary. Derived from a patch by Jakob Stoklund Olesen.
llvm-svn: 69635
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llvm-svn: 69624
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in the MachineFunction class, renaming it to addLiveIn for consistency with
the same method in MachineBasicBlock. Thanks for Anton for suggesting this.
llvm-svn: 69615
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llvm-svn: 69613
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llvm-svn: 69605
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llvm-svn: 69417
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llvm-svn: 69394
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llvm-svn: 69382
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llvm-svn: 69381
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punctuation. No functional changes.
llvm-svn: 69378
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for ARM. Patch by Sandeep Patel.
llvm-svn: 69371
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leaq foo@TLSGD(%rip), %rdi
as part of the instruction sequence. Using a register other than %rdi and then
copying it to %rdi is not valid.
llvm-svn: 69350
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llvm-svn: 69347
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matter, because this instruction isn't generated until after
things that care.
llvm-svn: 69336
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present, but it's inconsistent.
llvm-svn: 69335
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this fixes a crash on CodeGen/Generic/externally_available.ll
on ppc hosts. Thanks to Nicholas L for pointing this out.
llvm-svn: 69333
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llvm-svn: 69284
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llvm-svn: 69204
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llvm-svn: 69203
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llvm-svn: 69127
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the local register allocator.
llvm-svn: 69115
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either the source or destination is a physical h register.
This fixes sqlite3 with the post-RA scheduler enabled.
llvm-svn: 69111
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REX prefixes.
llvm-svn: 69108
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any non-address uses of the address value. This fixes 186.crafty.
llvm-svn: 69094
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llvm-svn: 69049
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llvm-svn: 69022
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it accordingly. Thanks to Jakob Stoklund Olesen for pointing
out how this might be useful.
llvm-svn: 68986
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Now debug_inlined section is covered by TAI->doesDwarfUsesInlineInfoSection(), which is false by default.
llvm-svn: 68964
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- Add patterns for h-register extract, which avoids a shift and mask,
and in some cases a temporary register.
- Add address-mode matching for turning (X>>(8-n))&(255<<n), where
n is a valid address-mode scale value, into an h-register extract
and a scaled-offset address.
- Replace X86's MOV32to32_ and related instructions with the new
target-independent COPY_TO_SUBREG instruction.
On x86-64 there are complicated constraints on h registers, and
CodeGen doesn't currently provide a high-level way to express all of them,
so they are handled with a bunch of special code. This code currently only
supports extracts where the result is used by a zero-extend or a store,
though these are fairly common.
These transformations are not always beneficial; since there are only
4 h registers, they sometimes require extra move instructions, and
this sometimes increases register pressure because it can force out
values that would otherwise be in one of those registers. However,
this appears to be relatively uncommon.
llvm-svn: 68962
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ISD::SIGN_EXTEND_INREG. Tablegen-generated code can handle
these cases, and the scheduling issues observed earlier
appear to be resolved now.
llvm-svn: 68959
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llvm-svn: 68958
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llvm-svn: 68954
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llvm-svn: 68951
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llvm-svn: 68950
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This unbreaks the JIT on x86-64.
llvm-svn: 68948
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llvm-svn: 68947
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getting passed. We couldn't catch this as we did not have tests that were passing an int value larger than 256.
llvm-svn: 68946
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to support C99 inline, GNU extern inline, etc. Related bugzilla's
include PR3517, PR3100, & PR2933. Nothing uses this yet, but it
appears to work.
llvm-svn: 68940
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only if symbolic addresses are RIP relatives.
llvm-svn: 68924
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llvm-svn: 68915
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See comment for details. This fixes rdar://6772169
llvm-svn: 68890
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llvm-svn: 68887
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