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* Fix (movhps load) lowering / pattern to match more cases. rdar://10050549Evan Cheng2011-08-312-3/+7
| | | | llvm-svn: 138848
* Some minor cleanups for r138845.Eli Friedman2011-08-311-22/+0
| | | | llvm-svn: 138846
* Some 64-bit atomic operations on ARM. 64-bit cmpxchg coming next.Eli Friedman2011-08-314-1/+277
| | | | llvm-svn: 138845
* Fix issues with disassembly of IT instructions involving condition codes ↵Owen Anderson2011-08-302-30/+32
| | | | | | other the EQ/NE. Discovered by roundtrip testing. llvm-svn: 138840
* Fix encoding of CBZ/CBNZ Thumb2 instructions with immediate offsets rather ↵Owen Anderson2011-08-301-1/+4
| | | | | | than labels. llvm-svn: 138837
* Fix encoding of PC-relative Thumb1 LDR's when using immediate offsets ↵Owen Anderson2011-08-301-1/+4
| | | | | | instead of labels. llvm-svn: 138835
* Fix encoding of Thumb1 B instructions with immediate offsets, which is ↵Owen Anderson2011-08-301-1/+4
| | | | | | necessary for round-tripping. llvm-svn: 138834
* Clean up whitespace.Owen Anderson2011-08-301-8/+8
| | | | llvm-svn: 138833
* Fix off-by-one error Benjamin noticed.Bill Wendling2011-08-301-1/+1
| | | | llvm-svn: 138832
* Enable compact unwind info by default. This only applies to Darwin when CFI isBill Wendling2011-08-301-9/+1
| | | | | | disabled. llvm-svn: 138826
* Fix C++0x narrowing errors when char is unsigned.Jeffrey Yasskin2011-08-301-2/+2
| | | | | | | In the case of EDInstInfo, this would actually cause a bug when -1 became 255 and was then compared >=0 in llvm-mc/Disassembler.cpp. llvm-svn: 138825
* Adds support for variable sized allocas. For a variable sized alloca,Rafael Espindola2011-08-302-15/+166
| | | | | | | | | | | | code is inserted to first check if the current stacklet has enough space. If so, space is allocated by simply decrementing the stack pointer. Otherwise a runtime routine (__morestack_allocate_stack_space in libgcc) is called which allocates the required memory from the heap. Patch by Sanjoy Das. llvm-svn: 138818
* Adds a SelectionDAG node X86SegAlloca which will be custom loweredRafael Espindola2011-08-304-0/+31
| | | | | | | | | | | | from DYNAMIC_STACKALLOC. Two new pseudo instructions (SEG_ALLOCA_32 and SEG_ALLOCA_64) which will match X86SegAlloca (based on word size) are also added. They will be custom emitted to inject the actual stack handling code. Patch by Sanjoy Das. llvm-svn: 138814
* Emit segmented-stack specific code into function prologues forRafael Espindola2011-08-304-3/+174
| | | | | | | | | | | | X86. Modify the pass added in the previous patch to call this new code. This new prologues generated will call a libgcc routine (__morestack) to allocate more stack space from the heap when required Patch by Sanjoy Das. llvm-svn: 138812
* Command line option to enable support for segmented stacks:Rafael Espindola2011-08-301-0/+7
| | | | | | | -segmented-stacks. Patch by Sanjoy Das! llvm-svn: 138811
* Follow up to r138791.Evan Cheng2011-08-304-2/+30
| | | | | | | | | | | | Add a instruction flag: hasPostISelHook which tells the pre-RA scheduler to call a target hook to adjust the instruction. For ARM, this is used to adjust instructions which may be setting the 's' flag. ADC, SBC, RSB, and RSC instructions have implicit def of CPSR (required since it now uses CPSR physical register dependency rather than "glue"). If the carry flag is used, then the target hook will *fill in* the optional operand with CPSR. Otherwise, the hook will remove the CPSR implicit def from the MachineInstr. llvm-svn: 138810
* Set CR1EQ only when lowering vararg floating arguments (not any varargRoman Divacky2011-08-302-2/+10
| | | | | | arguments as before), unset CR1EQ otherwise. llvm-svn: 138802
* Fix typos in SPUMCTargetDesc.hJames Molloy2011-08-301-2/+2
| | | | | | Patch supplied by Liu (projlc@gmail.com) llvm-svn: 138799
* Fix typo in BlackfinFrameLowering.hJames Molloy2011-08-301-2/+2
| | | | | | Patch supplied by Liu (projlc@gmail.com) llvm-svn: 138798
* Fix typo in MSP430MCTargetDesc.h.James Molloy2011-08-301-2/+2
| | | | | | Patch supplied by Liu (projlc@gmail.com) llvm-svn: 138797
* Fix typo in MipsMCTargetDesc.h; Patch supplied by Liu (proljc@gmail.com)James Molloy2011-08-301-4/+4
| | | | llvm-svn: 138796
* Change ARM / Thumb2 addc / adde and subc / sube modeling to use physicalEvan Cheng2011-08-307-346/+358
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | register dependency (rather than glue them together). This is general goodness as it gives scheduler more freedom. However it is motivated by a nasty bug in isel. When a i64 sub is expanded to subc + sube. libcall #1 \ \ subc \ / \ \ / \ \ / libcall #2 sube If the libcalls are not serialized (i.e. both have chains which are dag entry), legalizer can serialize them in arbitrary orders. If it's unlucky, it can force libcall #2 before libcall #1 in the above case. subc | libcall #2 | libcall #1 | sube However since subc and sube are "glued" together, this ends up being a cycle when the scheduler combine subc and sube as a single scheduling unit. The right solution is to fix LegalizeType too chains the libcalls together. However, LegalizeType is not processing nodes in order so that's harder than it should be. For now, the move to physical register dependency will do. rdar://10019576 llvm-svn: 138791
* Revert 138781. It's not playing nicely with the immediate forms for ADC.Jim Grosbach2011-08-291-20/+0
| | | | llvm-svn: 138782
* Thumb2 assembler aliases for ADC/SBC w/o the .w suffix.Jim Grosbach2011-08-291-0/+20
| | | | llvm-svn: 138781
* Add missing encoding information for some of the GPR<->FP register moves.Owen Anderson2011-08-291-2/+23
| | | | llvm-svn: 138780
* Thumb2 parsing and encoding for IT blocks.Jim Grosbach2011-08-291-23/+104
| | | | llvm-svn: 138773
* Explicitly zero out parts of a vector which are required to be zero by the ↵Eli Friedman2011-08-291-0/+3
| | | | | | algorithm in LowerUINT_TO_FP_i32. This only has a substantial effect on the generated code when the input is extracted from a vector register; other ways of loading an i32 do the appropriate zeroing implicitly. Fixes PR10802. llvm-svn: 138768
* Apply the same fix for the change in LDR_PRE_IMM/LDRB_PRE_IMM operand ↵Owen Anderson2011-08-291-1/+2
| | | | | | encodings to the load-store optimizer that I applied to the instruction selector in r138758. Fixes ary3 from the nightly test suite. llvm-svn: 138766
* Specify an additional fixed bit in the PLD/PLDW/PLI register-register encoding.Owen Anderson2011-08-291-0/+1
| | | | llvm-svn: 138760
* addrmode_imm12 and addrmode2_offset encode their immediate values ↵Owen Anderson2011-08-291-4/+28
| | | | | | differently. Update the manual instruction selection code that was encoding them the addrmode2 way even though LDR_PRE_IMM/LDRB_PRE_IMM had switched to addrmode_imm12. Should fix a number of nightly test failures. llvm-svn: 138758
* Improve handling of #-0 offsets for many more pre-indexed addressing modes.Owen Anderson2011-08-293-6/+15
| | | | llvm-svn: 138754
* Expand ATOMIC_LOAD and ATOMIC_STORE for architectures I don't know well ↵Eli Friedman2011-08-294-0/+10
| | | | | | enough to fix properly. llvm-svn: 138751
* Update the load-store optimizer for changes to the operands on LDR_PRE_IMM ↵Owen Anderson2011-08-291-4/+10
| | | | | | and LDRB_PRE_IMM in r138653. llvm-svn: 138746
* Move non-intruction patterns to a more appropriate place!Bruno Cardoso Lopes2011-08-291-31/+33
| | | | llvm-svn: 138744
* Add support for parsing #-0 on non-memory-operand immediate values, and add ↵Owen Anderson2011-08-291-2/+13
| | | | | | a testcase that necessitates it. llvm-svn: 138739
* Remove premature previous commit.Nicolas Geoffray2011-08-281-25/+7
| | | | llvm-svn: 138725
* Encoding of instructions referencing segments has changed. Do what ↵Nicolas Geoffray2011-08-281-7/+25
| | | | | | X86MCCodeEmitter does. llvm-svn: 138723
* Silence GCC warnings and make an array const.Benjamin Kramer2011-08-272-7/+6
| | | | llvm-svn: 138706
* Improve encoding support for BLX with immediat eoperands, and fix a BLX ↵Owen Anderson2011-08-264-12/+25
| | | | | | decoding bug this uncovered. llvm-svn: 138675
* Correct encoding of BL with immediate offset.Owen Anderson2011-08-261-5/+10
| | | | llvm-svn: 138673
* ARM assembly parsing tweak for pldw.Jim Grosbach2011-08-261-3/+4
| | | | llvm-svn: 138669
* Spelling fail.Owen Anderson2011-08-261-1/+1
| | | | llvm-svn: 138667
* Thumb2 assembler parsing and encoding of IT instruction.Jim Grosbach2011-08-262-12/+136
| | | | | | | | This handles only the handling of the IT instruction itself, not the processing and validation of the instructions in the IT block. That's next, and will include encoding tests for IT itself. llvm-svn: 138665
* Add support for generating CMPXCHG16B on x86-64 for the cmpxchg IR instruction.Eli Friedman2011-08-267-48/+94
| | | | llvm-svn: 138660
* Fix ARM codegen breakage caused by r138653.Owen Anderson2011-08-261-6/+15
| | | | llvm-svn: 138657
* invalid-LDR_PRE-arm.txt was already passing, but for the wrong reasons. We ↵Owen Anderson2011-08-266-19/+96
| | | | | | were failing to specify enough fixed bits of LDR_PRE/LDRB_PRE, resulting in decoding conflicts. Separate them into immediate vs. register versions, allowing us to specify the necessary fixed bits. This in turn results in the test being decoded properly, and being rejected as UNPREDICTABLE rather than a hard failure. llvm-svn: 138653
* Update for feedback from Jim.Owen Anderson2011-08-261-3/+3
| | | | llvm-svn: 138642
* ARMDisassembler: Always return a size, even when disassembling fails.Benjamin Kramer2011-08-261-3/+11
| | | | | | This should fix PR10772. llvm-svn: 138636
* Support an extension of ARM asm syntax to allow immediate operands to ADR ↵Owen Anderson2011-08-263-17/+36
| | | | | | instructions. This is helpful for disassembler testing, and indeed exposed a disassembler bug that is also fixed here. llvm-svn: 138635
* Don't insert branch hint lables that are never used. Kalle Raiskila2011-08-262-23/+0
| | | | llvm-svn: 138630
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