summaryrefslogtreecommitdiffstats
path: root/llvm/lib/Target
Commit message (Collapse)AuthorAgeFilesLines
...
* ARM: Fix encoding of hint instruction for Thumb.Quentin Colombet2013-04-264-16/+22
| | | | | | | | | | | | | | | "hint" space for Thumb actually overlaps the encoding space of the CPS instruction. In actuality, hints can be defined as CPS instructions where imod and M bits are all nil. Handle decoding of permitted nop-compatible hints (i.e. nop, yield, wfi, wfe, sev) in DecodeT2CPSInstruction. This commit adds a proper diagnostic message for Imm0_4 and updates all tests. Patch by Mihail Popa <Mihail.Popa@arm.com>. llvm-svn: 180617
* PowerPC: Use RegisterOperand instead of RegisterClass operandsUlrich Weigand2013-04-263-432/+452
| | | | | | | | | | | | | | | | | In the default PowerPC assembler syntax, registers are specified simply by number, so they cannot be distinguished from immediate values (without looking at the opcode). This means that the default operand matching logic for the asm parser does not work, and we need to specify custom matchers. Since those can only be specified with RegisterOperand classes and not directly on the RegisterClass, all instructions patterns used by the asm parser need to use a RegisterOperand (instead of a RegisterClass) for all their register operands. This patch adds one RegisterOperand for each RegisterClass, using the same name as the class, just in lower case, and updates all instruction patterns to use RegisterOperand instead of RegisterClass operands. llvm-svn: 180611
* PowerPC: Fix encoding of vsubcuw and vsum4sbs instructionsUlrich Weigand2013-04-261-2/+2
| | | | | | | | | When testing the asm parser, I noticed wrong encodings for the above instructions (wrong sub-opcodes). Tests will be added together with the asm parser. llvm-svn: 180608
* PowerPC: Fix encoding of stfsu and stfdu instructionsUlrich Weigand2013-04-261-2/+2
| | | | | | | | | | | When testing the asm parser, I noticed wrong encodings for the above instructions (wrong sub-opcodes). Note that apparently the compiler currently never generates pre-inc instructions for floating point types for some reason ... Tests will be added together with the asm parser. llvm-svn: 180607
* PowerPC: Fix encoding of rldimi and rldcl instructionsUlrich Weigand2013-04-263-3/+36
| | | | | | | | | | When testing the asm parser, I noticed wrong encodings for the above instructions (wrong operand name in rldimi, wrong form and sub-opcode for rldcl). Tests will be added together with the asm parser. llvm-svn: 180606
* PowerPC: Support PC-relative fixup_ppc_brcond14.Ulrich Weigand2013-04-261-0/+3
| | | | | | | | When testing the asm parser, I ran into an error when using a conditional branch to an external symbol (this doesn't occur in compiler-generated code) due to missing support in PPCELFObjectWriter::getRelocTypeInner. llvm-svn: 180605
* ARM/NEON: Pattern match vector integer abs to vabs.Benjamin Kramer2013-04-261-0/+23
| | | | llvm-svn: 180604
* X86: Now that we have a canonical form for vector integer abs, match it into ↵Benjamin Kramer2013-04-261-0/+51
| | | | | | pabs. llvm-svn: 180600
* Mips assembler: .set reorder supportJack Carter2013-04-251-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | Mips have delayslots for certain instructions like jumps and branches. These are instructions that follow the branch or jump and are executed before the jump or branch is completed. Early Mips compilers could not cope with delayslots and left them up to the assembler. The assembler would fill the delayslots with the appropriate instruction, usually just a nop to allow correct runtime behavior. The default behavior for this is set with .set reorder. To tell the assembler that you don't want it to mess with the delayslot one used .set noreorder. For backwards compatibility we need to support .set reorder and have it be the default behavior in the assembler. Our support for it is to insert a NOP directly after an instruction with a delayslot when in .set reorder mode. Contributer: Vladimir Medic llvm-svn: 180584
* Make function documentation conform to llvm standards.Preston Gurd2013-04-251-30/+32
| | | | | | Expunge all remaining traces and use of live variable information. llvm-svn: 180577
* ARM cost model: Integer div and rem is lowered to a function callArnold Schwaighofer2013-04-251-0/+68
| | | | | | | | Reflect this in the cost model. I observed this in MiBench/consumer-lame. radar://13354716 llvm-svn: 180576
* This patch adds the X86FixupLEAs pass, which will reduce instructionPreston Gurd2013-04-257-0/+270
| | | | | | | | latency for certain models of the Intel Atom family, by converting instructions into their equivalent LEA instructions, when it is both useful and possible to do so. llvm-svn: 180573
* Fix section relocation for SECTIONREL32 with immediate offset.Rafael Espindola2013-04-251-2/+15
| | | | | | Patch by Kai Nacke. This matches the gnu as output. llvm-svn: 180568
* [mips] Add definitions of micromips load and store instructions.Akira Hatanaka2013-04-254-17/+43
| | | | | | Patch by Zoran Jovanovic. llvm-svn: 180241
* [mips] Add definitions of micromips shift instructions.Akira Hatanaka2013-04-254-12/+62
| | | | | | Patch by Zoran Jovanovic. llvm-svn: 180238
* R600: Initialize BooleanVectorContentsTom Stellard2013-04-241-0/+1
| | | | | | Fixes test/CodeGen/R600/setcc.ll llvm-svn: 180231
* R600: Use SHT_PROGBITS for the .AMDGPU.config sectionTom Stellard2013-04-241-1/+1
| | | | | | | | The libelf implementation that is distributed here: http://www.mr511.de/software/english.html will not parse sections that are marked SHT_NULL. llvm-svn: 180230
* Hexagon: Use multiclass for combine and STri[bhwd]_shl_V4 instructions.Jyotsna Verma2013-04-232-176/+149
| | | | llvm-svn: 180145
* Hexagon: Define relations for GP-relative instructions.Jyotsna Verma2013-04-231-15/+17
| | | | | | No functionality change. llvm-svn: 180144
* Add more tests for r179925 to verify correct handling of signext/zeroext; ↵Stephen Lin2013-04-231-3/+6
| | | | | | strengthen condition check to require actual MVT::i32 virtual register types, just in case (no actual functionality change) llvm-svn: 180138
* Lowercase "is" boolean variable prefix for consistency within function, no ↵Stephen Lin2013-04-231-12/+12
| | | | | | functionality change. llvm-svn: 180136
* Hexagon: Remove assembler mapped instruction definitions.Jyotsna Verma2013-04-235-108/+80
| | | | llvm-svn: 180133
* Change commentary for PowerPC Boolean vector contents.Bill Schmidt2013-04-231-1/+2
| | | | | | No functional change intended. llvm-svn: 180131
* [mips] Compare splat value with element size instead of calling isUIntN.Akira Hatanaka2013-04-231-2/+2
| | | | | | No intended changes in functionality. llvm-svn: 180130
* DAGCombine should not aggressively fold SEXT(VSETCC(...)) into a wider ↵Owen Anderson2013-04-231-1/+1
| | | | | | | | | VSETCC without first checking the target's vector boolean contents. This exposed an issue with PowerPC AltiVec where it appears it was setting the wrong vector boolean contents. The included change fixes the PowerPC tests, and was OK'd by Hal. llvm-svn: 180129
* R600: Use .AMDGPU.config section to emit stacksizeVincent Lejeune2013-04-235-16/+25
| | | | llvm-svn: 180124
* R600: Add CF_ENDVincent Lejeune2013-04-233-44/+77
| | | | llvm-svn: 180123
* Hexagon: Remove duplicate instructions to handle global/immediate valuesJyotsna Verma2013-04-232-321/+55
| | | | | | for absolute/absolute-set addressing modes. llvm-svn: 180120
* AArch64: remove unnecessary check that RS is validTim Northover2013-04-231-2/+3
| | | | | | | | AArch64 always demands a register-scavenger, so the pointer should never be NULL. However, in the spirit of paranoia, we'll assert it before use just in case. llvm-svn: 180080
* Remove unused DwarfSectionOffsetDirective stringMatt Arsenault2013-04-221-2/+0
| | | | | | | The value isn't actually used, and setting it emits a COFF specific directive. llvm-svn: 180064
* Move C++ code out of the C headers and into either C++ headersEric Christopher2013-04-222-0/+48
| | | | | | | or the C++ files themselves. This enables people to use just a C compiler to interoperate with LLVM. llvm-svn: 180063
* [ms-inline asm] Removed this unnecessary check. In the current implementation,Chad Rosier2013-04-221-1/+1
| | | | | | Disp will always be one of MCSymbolRefExpr or MCConstantExpr, and never NULL. llvm-svn: 180059
* [ms-inline asm] Add the OpDecl to the InlineAsmIdentifierInfo struct and in turnChad Rosier2013-04-221-13/+18
| | | | | | | the MCParsedAsmOperand. Part of rdar://13663589 llvm-svn: 180054
* Fix unused variable warning.Chad Rosier2013-04-221-1/+1
| | | | llvm-svn: 180044
* 80 columns.Akira Hatanaka2013-04-223-6/+9
| | | | llvm-svn: 180040
* [mips] In performDSPShiftCombine, check that all elements in the vector areAkira Hatanaka2013-04-222-10/+12
| | | | | | | shifted by the same amount and the shift amount is smaller than the element size. llvm-svn: 180039
* [ms-inline asm] Remove the identifier parsing logic from the AsmParser. This isChad Rosier2013-04-221-61/+55
| | | | | | | | now taken care of by the frontend, which allows us to parse arbitrary C/C++ variables. Part of rdar://13663589 llvm-svn: 180037
* [ms-inline asm] Refactor/clean up the SemaLookup interface. No functionalChad Rosier2013-04-221-34/+23
| | | | | | | change indended. Part of rdar://13663589 llvm-svn: 180028
* No really, don't store anything to this since it's unconditionallyEric Christopher2013-04-221-1/+1
| | | | | | set below. llvm-svn: 180015
* Remove variable store that is never read.Eric Christopher2013-04-221-1/+1
| | | | llvm-svn: 180014
* Fix for 5.5 Parameter Passing --> Stage C:Stepan Dyatkovskiy2013-04-223-2/+8
| | | | | | | | | | | | | | | -- C.4 and C.5 statements, when NSAA is not equal to SP. -- C.1.cp statement for VA functions. Note: There are no VFP CPRCs in a variadic procedure. Before this patch "NSAA != 0" means "don't use GPRs anymore ". But there are some exceptions in AAPCS. 1. For non VA function: allocate all VFP regs for CPRC. When all VFPs are allocated CPRCs would be sent to stack, while non CPRCs may be still allocated in GRPs. 2. Check that for VA functions all params uses GPRs and then stack. No exceptions, no CPRCs here. llvm-svn: 180011
* Legalize vector truncates by parts rather than just splitting.Jim Grosbach2013-04-211-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than just splitting the input type and hoping for the best, apply a bit more cleverness. Just splitting the types until the source is legal often leads to an illegal result time, which is then widened and a scalarization step is introduced which leads to truly horrible code generation. With the loop vectorizer, these sorts of operations are much more common, and so it's worth extra effort to do them well. Add a legalization hook for the operands of a TRUNCATE node, which will be encountered after the result type has been legalized, but if the operand type is still illegal. If simple splitting of both types ends up with the result type of each half still being legal, just do that (v16i16 -> v16i8 on ARM, for example). If, however, that would result in an illegal result type (v8i32 -> v8i8 on ARM, for example), we can get more clever with power-two vectors. Specifically, split the input type, but also widen the result element size, then concatenate the halves and truncate again. For example on ARM, To perform a "%res = v8i8 trunc v8i32 %in" we transform to: %inlo = v4i32 extract_subvector %in, 0 %inhi = v4i32 extract_subvector %in, 4 %lo16 = v4i16 trunc v4i32 %inlo %hi16 = v4i16 trunc v4i32 %inhi %in16 = v8i16 concat_vectors v4i16 %lo16, v4i16 %hi16 %res = v8i8 trunc v8i16 %in16 This allows instruction selection to generate three VMOVN instructions instead of a sequences of moves, stores and loads. Update the ARMTargetTransformInfo to take this improved legalization into account. Consider the simplified IR: define <16 x i8> @test1(<16 x i32>* %ap) { %a = load <16 x i32>* %ap %tmp = trunc <16 x i32> %a to <16 x i8> ret <16 x i8> %tmp } define <8 x i8> @test2(<8 x i32>* %ap) { %a = load <8 x i32>* %ap %tmp = trunc <8 x i32> %a to <8 x i8> ret <8 x i8> %tmp } Previously, we would generate the truly hideous: .syntax unified .section __TEXT,__text,regular,pure_instructions .globl _test1 .align 2 _test1: @ @test1 @ BB#0: push {r7} mov r7, sp sub sp, sp, #20 bic sp, sp, #7 add r1, r0, #48 add r2, r0, #32 vld1.64 {d24, d25}, [r0:128] vld1.64 {d16, d17}, [r1:128] vld1.64 {d18, d19}, [r2:128] add r1, r0, #16 vmovn.i32 d22, q8 vld1.64 {d16, d17}, [r1:128] vmovn.i32 d20, q9 vmovn.i32 d18, q12 vmov.u16 r0, d22[3] strb r0, [sp, #15] vmov.u16 r0, d22[2] strb r0, [sp, #14] vmov.u16 r0, d22[1] strb r0, [sp, #13] vmov.u16 r0, d22[0] vmovn.i32 d16, q8 strb r0, [sp, #12] vmov.u16 r0, d20[3] strb r0, [sp, #11] vmov.u16 r0, d20[2] strb r0, [sp, #10] vmov.u16 r0, d20[1] strb r0, [sp, #9] vmov.u16 r0, d20[0] strb r0, [sp, #8] vmov.u16 r0, d18[3] strb r0, [sp, #3] vmov.u16 r0, d18[2] strb r0, [sp, #2] vmov.u16 r0, d18[1] strb r0, [sp, #1] vmov.u16 r0, d18[0] strb r0, [sp] vmov.u16 r0, d16[3] strb r0, [sp, #7] vmov.u16 r0, d16[2] strb r0, [sp, #6] vmov.u16 r0, d16[1] strb r0, [sp, #5] vmov.u16 r0, d16[0] strb r0, [sp, #4] vldmia sp, {d16, d17} vmov r0, r1, d16 vmov r2, r3, d17 mov sp, r7 pop {r7} bx lr .globl _test2 .align 2 _test2: @ @test2 @ BB#0: push {r7} mov r7, sp sub sp, sp, #12 bic sp, sp, #7 vld1.64 {d16, d17}, [r0:128] add r0, r0, #16 vld1.64 {d20, d21}, [r0:128] vmovn.i32 d18, q8 vmov.u16 r0, d18[3] vmovn.i32 d16, q10 strb r0, [sp, #3] vmov.u16 r0, d18[2] strb r0, [sp, #2] vmov.u16 r0, d18[1] strb r0, [sp, #1] vmov.u16 r0, d18[0] strb r0, [sp] vmov.u16 r0, d16[3] strb r0, [sp, #7] vmov.u16 r0, d16[2] strb r0, [sp, #6] vmov.u16 r0, d16[1] strb r0, [sp, #5] vmov.u16 r0, d16[0] strb r0, [sp, #4] ldm sp, {r0, r1} mov sp, r7 pop {r7} bx lr Now, however, we generate the much more straightforward: .syntax unified .section __TEXT,__text,regular,pure_instructions .globl _test1 .align 2 _test1: @ @test1 @ BB#0: add r1, r0, #48 add r2, r0, #32 vld1.64 {d20, d21}, [r0:128] vld1.64 {d16, d17}, [r1:128] add r1, r0, #16 vld1.64 {d18, d19}, [r2:128] vld1.64 {d22, d23}, [r1:128] vmovn.i32 d17, q8 vmovn.i32 d16, q9 vmovn.i32 d18, q10 vmovn.i32 d19, q11 vmovn.i16 d17, q8 vmovn.i16 d16, q9 vmov r0, r1, d16 vmov r2, r3, d17 bx lr .globl _test2 .align 2 _test2: @ @test2 @ BB#0: vld1.64 {d16, d17}, [r0:128] add r0, r0, #16 vld1.64 {d18, d19}, [r0:128] vmovn.i32 d16, q8 vmovn.i32 d17, q9 vmovn.i16 d16, q8 vmov r0, r1, d16 bx lr llvm-svn: 179989
* Passing arguments to varags functions under the SPARC v9 ABI.Jakob Stoklund Olesen2013-04-211-0/+47
| | | | | | | Arguments after the fixed arguments never use the floating point registers. llvm-svn: 179987
* Fix the SETHIimm pattern for 64-bit code.Jakob Stoklund Olesen2013-04-211-2/+1
| | | | | | Don't ignore the high 32 bits of the immediate. llvm-svn: 179985
* ARM: Use ldrd/strd to spill 64-bit pairs when available.Tim Northover2013-04-213-37/+106
| | | | | | | This allows common sp-offsets to be part of the instruction and is probably faster on modern CPUs too. llvm-svn: 179977
* Compile varargs functions for SPARCv9.Jakob Stoklund Olesen2013-04-201-31/+57
| | | | | | | | | | | | With a little help from the frontend, it looks like the standard va_* intrinsics can do the job. Also clean up an old bitcast hack in LowerVAARG that dealt with unaligned double loads. Load SDNodes can specify an alignment now. Still missing: Calling varargs functions with float arguments. llvm-svn: 179961
* ARM: don't add FrameIndex offset for LDMIA (has no immediate)Tim Northover2013-04-201-1/+1
| | | | | | | | | | | | Previously, when spilling 64-bit paired registers, an LDMIA with both a FrameIndex and an offset was produced. This kind of instruction shouldn't exist, and the extra operand was being confused with the predicate, causing aborts later on. This removes the invalid 0-offset from the instruction being produced. llvm-svn: 179956
* AArch64: remove useless commentTim Northover2013-04-201-2/+0
| | | | llvm-svn: 179952
* Remove unused ShouldFoldAtomicFences flag.Tim Northover2013-04-203-13/+0
| | | | | | | | I think it's almost impossible to fold atomic fences profitably under LLVM/C++11 semantics. As a result, this is now unused and just cluttering up the target interface. llvm-svn: 179940
* Remove unused MEMBARRIER DAG node; it's been replaced by ATOMIC_FENCE.Tim Northover2013-04-2011-113/+1
| | | | llvm-svn: 179939
OpenPOWER on IntegriCloud