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* Merge MCELF.h into MCSymbolELF.h.Rafael Espindola2015-06-0213-63/+62
| | | | | | | Now that we have a dedicated type for ELF symbol, these helper functions can become member function of MCSymbolELF. llvm-svn: 238864
* AArch64: fix typo in SMIN far atomics and add testsTim Northover2015-06-021-1/+1
| | | | llvm-svn: 238858
* Push constness through LoopInfo::isLoopHeader and clean it up a bit.Benjamin Kramer2015-06-021-2/+1
| | | | | | NFC. llvm-svn: 238843
* make reciprocal estimate code generation more flexible by adding ↵Sanjay Patel2015-06-027-54/+267
| | | | | | | | | | | | | | | | | | | command-line options (2nd try) The first try (r238051) to land this was reverted due to bot failures that were hopefully addressed by r238788. This patch adds a TargetRecip class for processing many recip codegen possibilities. The class is intended to handle both command-line options to llc as well as options passed in from a front-end such as clang with the -mrecip option. The x86 backend is updated to use the new functionality. Only -mcpu=btver2 with -ffast-math should see a functional change from this patch. All other x86 CPUs continue to *not* use reciprocal estimates by default with -ffast-math. Differential Revision: http://reviews.llvm.org/D8982 llvm-svn: 238842
* AVX-512: Implemented VRANGESD and VRANGESS instructions for SKX Implemented ↵Elena Demikhovsky2015-06-021-0/+7
| | | | | | | | | | DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238834
* AVX-512: Shorten implementation of lowerV16X32VectorShuffle()Elena Demikhovsky2015-06-021-39/+61
| | | | | | | using lowerVectorShuffleWithSHUFPS() and other shuffle-helpers routines. Added matching of VALIGN instruction. llvm-svn: 238830
* [mips] Add support for dynamic stack realignment.Vasileios Kalintiris2015-06-028-8/+141
| | | | | | | | | | | | | | | | | | | | Summary: With this change we are able to realign the stack dynamically, whenever it contains objects with alignment requirements that are larger than the alignment specified from the given ABI. We have to use the $fp register as the frame pointer when we perform dynamic stack realignment. In complex stack frames, with variably-sized objects, we reserve additionally the callee-saved register $s7 as the base pointer in order to reference locals. Reviewers: dsanders Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8633 llvm-svn: 238829
* Revert "ARM: Thumb2 LDRD/STRD supports independent input/output regs"Renato Golin2015-06-021-22/+20
| | | | | | | | | This reverts commit r238795, as it broke the Thumb2 self-hosting buildbot. Since self-hosting issues with Clang are hard to investigate, I'm taking the liberty to revert now, so we can investigate it offline. llvm-svn: 238821
* [AArch64] Add v8.1a atomic instructionsVladimir Sukharev2015-06-028-5/+432
| | | | | | | | | | | | Patch by: Tom Coxon Reviewers: t.p.northover Subscribers: llvm-commits Differential Revision: http://reviews.llvm.org/D8501 llvm-svn: 238818
* [mips] [IAS] Add support for the .set softfloat/hardfloat directives.Toma Tabacu2015-06-023-0/+48
| | | | | | | | | | | | | | Summary: These directives are used to set the current value of the SoftFloat feature. Reviewers: dsanders Reviewed By: dsanders Subscribers: llvm-commits, mpf Differential Revision: http://reviews.llvm.org/D9074 llvm-svn: 238813
* AVX-512: Implemented VFIXUPIMMSD and VFIXUPIMMSS instructions for KNLElena Demikhovsky2015-06-021-14/+51
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238811
* revert 238809Asaf Badouh2015-06-025-107/+25
| | | | llvm-svn: 238810
* AVX-512: Implemented GETEXP instruction for KNL and SKXAsaf Badouh2015-06-025-25/+107
| | | | | | | Added rounding mode modifier for SQRTPS/PD Added tests for encoding and intrinsics. llvm-svn: 238809
* Create a MCSymbolELF.Rafael Espindola2015-06-022-5/+7
| | | | | | | | | This create a MCSymbolELF class and moves SymbolSize since only ELF needs a size expression. This reduces the size of MCSymbol from 56 to 48 bytes. llvm-svn: 238801
* ARM: Thumb2 LDRD/STRD supports independent input/output regsMatthias Braun2015-06-011-20/+22
| | | | | | | | | | | | | The existing code would unnecessarily break LDRD/STRD apart with non-adjacent registers, on thumb2 this is not necessary. Ideally on thumb2 we shouldn't match for ldrd/strd pre-regalloc anymore as there is not reason to set register hints anymore, changing that is something for a future patch however. Differential Revision: http://reviews.llvm.org/D9694 llvm-svn: 238795
* AArch64: Use CMP;CCMP sequences for and/or/setcc trees.Matthias Braun2015-06-014-72/+255
| | | | | | | | | | | | Previously CCMP/FCCMP instructions were only used by the AArch64ConditionalCompares pass for control flow. This patch uses them for SELECT like instructions as well by matching patterns in ISelLowering. PR20927, rdar://18326194 Differential Revision: http://reviews.llvm.org/D8232 llvm-svn: 238793
* [bpf] fix buildAlexei Starovoitov2015-06-011-2/+2
| | | | | | | | fix breakage due to r238634 Patch by Vijay Subramanian. llvm-svn: 238792
* R600/SI: Don't hardcode pointer typeMatt Arsenault2015-06-011-4/+5
| | | | llvm-svn: 238789
* ARMLoadStoreOptimizer: Fix doxygen comments; NFCMatthias Braun2015-06-011-34/+28
| | | | llvm-svn: 238784
* Revert "[Hexagon] Adding basic ELF relocation generation and testing ↵Rafael Espindola2015-06-013-427/+28
| | | | | | | | | | | | advanced relaxation codepath." This reverts commit r238748. It broke the msan bot: http://lab.llvm.org:8011/builders/sanitizer-x86_64-linux-fast/builds/4372/steps/check-llvm%20msan/logs/stdio llvm-svn: 238772
* [mips][FastISel] Implement bswap.Vasileios Kalintiris2015-06-011-0/+64
| | | | | | | | | | | | | | | | | | Summary: Implement bswap intrinsic for MIPS FastISel. It's very different for misp32 r1/r2 . Based on a patch by Reed Kotler. Test Plan: bswap1.ll test-suite Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7219 llvm-svn: 238760
* [mips][FastISel] Implement intrinsics memset, memcopy & memmove.Vasileios Kalintiris2015-06-011-7/+89
| | | | | | | | | | | | | | | | | | | | Summary: Implement the intrinsics memset, memcopy and memmove in MIPS FastISel. Make some needed infrastructure fixes so that this can work. Based on a patch by Reed Kotler. Test Plan: memtest1.ll The patch passes test-suite for mips32 r1/r2 and at O0/O2 Reviewers: rkotler, dsanders Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7158 llvm-svn: 238759
* [mips][FastISel] Implement srem/urem and sdiv/udiv instructions.Vasileios Kalintiris2015-06-011-0/+61
| | | | | | | | | | | | | | | | | | | Summary: Implement the LLVM assembly urem/srem and sdiv/udiv instructions in MIPS FastISel. Based on a patch by Reed Kotler. Test Plan: srem1.ll div1.ll test-suite at O0/O2 for mips32 r1/r2 Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D7028 llvm-svn: 238757
* [mips][FastISel] Implement the select statement for MIPS FastISel.Vasileios Kalintiris2015-06-011-0/+47
| | | | | | | | | | | | | | | | | | Summary: Implement the LLVM IR select statement for MIPS FastISelsel. Based on a patch by Reed Kotler. Test Plan: "Make check" test included now. Passes test-suite at O2/O0 mips32 r1/r2. Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D6774 llvm-svn: 238756
* [mips][FastISel] Clobber HI0/LO0 registers in MUL instructions.Vasileios Kalintiris2015-06-011-0/+33
| | | | | | | | | | | | | | | | | | | | | Summary: The contents of the HI/LO registers are unpredictable after the execution of the MUL instruction. In addition to implicitly defining these registers in the MUL instruction definition, we have to mark those registers as dead too. Without this the fast register allocator is running out of registers when the MUL instruction is followed by another one that tries to allocate the AC0 register. Based on a patch by Reed Kotler. Reviewers: dsanders, rkotler Subscribers: llvm-commits, rfuhler Differential Revision: http://reviews.llvm.org/D9825 llvm-svn: 238755
* Fix relocation selection for foo-. on mips.Rafael Espindola2015-06-011-1/+1
| | | | | | This handles only the 32 bit case. llvm-svn: 238751
* Simplify code, NFC.Rafael Espindola2015-06-011-107/+60
| | | | llvm-svn: 238750
* [Hexagon] Adding basic ELF relocation generation and testing advanced ↵Colin LeMahieu2015-06-013-28/+427
| | | | | | relaxation codepath. llvm-svn: 238748
* AVX-512: Optimized vector shuffle for v16f32 and v16i32 types.Elena Demikhovsky2015-06-011-36/+48
| | | | llvm-svn: 238743
* Re-commit of r238201 with fix for building with shared libraries.Luke Cheeseman2015-06-017-18/+629
| | | | llvm-svn: 238739
* AVX-512: Implemented VRANGEPD and VRANGEPD instructions for SKX.Elena Demikhovsky2015-06-014-6/+34
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for encoding. By Igor Breger (igor.breger@intel.com) llvm-svn: 238738
* AVX-512: Implemented vector shuffle lowering for v8i64 and v8f64 types.Elena Demikhovsky2015-06-011-33/+102
| | | | | | I removed the vector-shuffle-512-v8.ll, it is auto-generated test, not valid any more. llvm-svn: 238735
* AVX-512: added all forms of VPSHUFD and VPSHUFHW, VPSHUFLWElena Demikhovsky2015-06-012-36/+28
| | | | | | including encodings. llvm-svn: 238729
* AVX-512: Implemented VFIXUPIMMPD and VFIXUPIMMPS instructions for KNL and SKXElena Demikhovsky2015-06-014-0/+74
| | | | | | | | | Implemented DAG lowering for all these forms. Added tests for encoding. by Igor Breger (igor.breger@intel.com) llvm-svn: 238728
* AVX-512: Fixed a bug in compress and expand intrinsics.Elena Demikhovsky2015-06-011-5/+8
| | | | | | By Igor Breger (igor.breger@intel.com) llvm-svn: 238724
* Add address space argument to isLegalAddressingModeMatt Arsenault2015-06-0120-27/+49
| | | | | | | | | | This is important because of different addressing modes depending on the address space for GPU targets. This only adds the argument, and does not update any of the uses to provide the correct address space. llvm-svn: 238723
* Simplify another function that doesn't fail.Rafael Espindola2015-06-011-1/+1
| | | | llvm-svn: 238703
* ARMConstantIslandPass.cpp: Prune an empty \brief. [-Wdocumentation]NAKAMURA Takumi2015-05-311-1/+0
| | | | llvm-svn: 238697
* [Hexagon] Including raw_ostream for debug builds.Colin LeMahieu2015-05-311-0/+1
| | | | llvm-svn: 238695
* [Hexagon] classes are actually structs.Colin LeMahieu2015-05-311-2/+2
| | | | llvm-svn: 238694
* [Hexagon] Adding MC packet shuffler.Colin LeMahieu2015-05-319-6/+882
| | | | llvm-svn: 238692
* ARM: recommit r237590: allow jump tables to be placed as constant islands.Tim Northover2015-05-317-238/+418
| | | | | | | | | | | | | | | The original version didn't properly account for the base register being modified before the final jump, so caused miscompilations in Chromium and LLVM. I've fixed this and tested with an LLVM self-host (I don't have the means to build & test Chromium). The general idea remains the same: in pathological cases jump tables can be too far away from the instructions referencing them (like other constants) so they need to be movable. Should fix PR23627. llvm-svn: 238680
* [Hexagon] Adding override specifier and removing erroneous assertionColin LeMahieu2015-05-301-4/+2
| | | | llvm-svn: 238664
* [Hexagon] Adding basic relaxation functionality.Colin LeMahieu2015-05-303-6/+157
| | | | llvm-svn: 238660
* Stripped trailing whitespace. NFC.Simon Pilgrim2015-05-301-12/+12
| | | | llvm-svn: 238654
* Comment change. NFCRenato Golin2015-05-301-3/+2
| | | | | | | That comment misleads the current discussions in mentioned bug. Leave the discussions to the bug. Also, adding a future change FIXME. llvm-svn: 238653
* [x86] Unify the horizontal adding used for popcount lowering taking theChandler Carruth2015-05-301-76/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | best approach of each. For vNi16, we use SHL + ADD + SRL pattern that seem easily the best. For vNi32, we use the PUNPCK + PSADBW + PACKUSWB pattern. In some cases there is a huge improvement with this in IACA's estimated throughput -- over 2x higher throughput!!!! -- but the measurements are too good to be true. In one narrow case, the SHL + ADD + SHL + ADD + SRL pattern looks slightly faster, but I'm not sure I believe any of the measurements at this point. Both are the exact same uops though. Hard to be confident of anything past that. If anyone wants to collect very detailed (Agner-level) timings with the result of this patch, or with the i32 case replaced with SHL + ADD + SHl + ADD + SRL, I'd be very interested. Note that you'll need to test it on both Ivybridge and Haswell, with both SSE3, SSSE3, and AVX selected as I saw unique behavior in each of these buckets with IACA all of which should be checked against measured performance. But this patch is still a useful improvement by dropping duplicate work and getting the much nicer PSADBW lowering for v2i64. I'd still like to rephrase this in terms of generic horizontal sum. It's a bit lame to have a special case of that just for popcount. llvm-svn: 238652
* [ARMTargetParser] Move IAS arch ext parser. NFCRenato Golin2015-05-301-20/+22
| | | | | | | | | | | The plan was to move the whole table into the already existing ArchExtNames but some fields depend on a table-generated file, and we don't yet have this feature in the generic lib/Support side. Once the minimum target-specific table-generated files are available in a generic fashion to these libraries, we'll have to keep it in the ASM parser. llvm-svn: 238651
* [x86] Split out the horizontal byte sum lowering component of the LUTChandler Carruth2015-05-301-78/+100
| | | | | | | | lowering into a helper function. NFC. llvm-svn: 238650
* [x86] Replace the long spelling of getting a bitcast with the *much*Chandler Carruth2015-05-301-332/+300
| | | | | | | | | | shorter one. NFC. In addition to being much shorter to type and requiring fewer arguments, this change saves over 30 lines from this one file, all wasted on total boilerplate... llvm-svn: 238640
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